Update yosys; rework AST_GENBLOCK's handling (#2502)

This PR updates yosys and adjusts synlig to it:

* rework the way, that synlig handles AST_GENBLOCK's,
* allow typedefing nested structs and unions inside AST_GENBLOCK's,
* add new simple tests,
* minor bugfixes.

frontends/systemverilog/uhdm_ast.cc

@@ -61,6 +61,7 @@ static IdString is_simplified_wire;
 static IdString low_high_bound;
 static IdString is_type_parameter;
 static IdString is_elaborated_module;
+static IdString expand_genblock;
 }; // namespace attr_id
 
 // TODO(mglb): use attr_id::* directly everywhere and remove those methods.
@@ -95,6 +96,7 @@ void attr_id_init()
     attr_id::low_high_bound = MAKE_INTERNAL_ID(low_high_bound);
     attr_id::is_type_parameter = MAKE_INTERNAL_ID(is_type_parameter);
     attr_id::is_elaborated_module = MAKE_INTERNAL_ID(is_elaborated_module);
+    attr_id::expand_genblock = MAKE_INTERNAL_ID(expand_genblock);
 }
 
 void attr_id_cleanup()
@@ -109,6 +111,7 @@ void attr_id_cleanup()
     attr_id::partial = IdString();
     attr_id::is_type_parameter = IdString();
     attr_id::is_elaborated_module = IdString();
+    attr_id::expand_genblock = IdString();
     attr_id::already_initialized = false;
 }
 
@@ -151,7 +154,8 @@ static void delete_internal_attributes(AST::AstNode *node)
         return;
 
     for (auto &attr : {UhdmAst::partial(), UhdmAst::packed_ranges(), UhdmAst::unpacked_ranges(), UhdmAst::force_convert(), UhdmAst::is_imported(),
-                       UhdmAst::is_simplified_wire(), UhdmAst::low_high_bound(), attr_id::is_type_parameter, attr_id::is_elaborated_module}) {
+                       UhdmAst::is_simplified_wire(), UhdmAst::low_high_bound(), attr_id::is_type_parameter, attr_id::is_elaborated_module,
+                       attr_id::expand_genblock}) {
         delete_attribute(node, attr);
     }
 }
@@ -1313,6 +1317,30 @@ static void simplify_format_string(AST::AstNode *current_node)
     current_node->children[0] = AST::AstNode::mkconst_str(preformatted_string);
 }
 
+void resolve_children_reparent(AST::AstNode *current_node)
+{
+    bool have_children_to_reparent = false;
+    for (AST::AstNode *child : current_node->children) {
+        if (child->attributes.count(attr_id::expand_genblock)) {
+            have_children_to_reparent = true;
+        }
+    }
+    if (!have_children_to_reparent)
+        return;
+    std::vector<AST::AstNode *> reparented;
+    for (AST::AstNode *child : current_node->children) {
+        if (child->attributes.count(attr_id::expand_genblock)) {
+            for (AST::AstNode *grandchild : child->children)
+                reparented.push_back(grandchild);
+            child->children.clear();
+            delete child;
+        } else {
+            reparented.push_back(child);
+        }
+    }
+    current_node->children = reparented;
+}
+
 // A wrapper for Yosys simplify function.
 // Simplifies AST constructs specific to this plugin to a form understandable by Yosys' simplify and then calls the latter if necessary.
 // Since simplify from Yosys has been forked to this codebase, all new code should be added there instead.
@@ -1370,10 +1398,26 @@ static void simplify_sv(AST::AstNode *current_node, AST::AstNode *parent_node)
         delete expanded;
         expanded = nullptr;
     }
+
+    if (current_node->attributes.count(attr_id::expand_genblock)) {
+        log_assert(current_node->str != "");
+        auto backup_scope = AST_INTERNAL::current_scope;
+
+        AST_INTERNAL::current_scope[current_node->str] = current_node;
+        synlig_expand_genblock(current_node, current_node->str + ".", false);
+        current_node->str = "";
+
+        std::swap(AST_INTERNAL::current_scope, backup_scope);
+        backup_scope.clear();
+    }
+
     // First simplify children
     for (size_t i = 0; i < current_node->children.size(); i++) {
         simplify_sv(current_node->children[i], current_node);
     }
+
+    resolve_children_reparent(current_node);
+
     switch (current_node->type) {
     case AST::AST_TYPEDEF:
     case AST::AST_ENUM:
@@ -4587,6 +4631,9 @@ void UhdmAst::process_gen_scope_array()
         genscope_node->children.clear();
         delete genscope_node;
     });
+    if (current_node->str != "") {
+        set_attribute(current_node, attr_id::expand_genblock, AST::AstNode::mkconst_int(1, true));
+    }
 }
 
 void UhdmAst::process_tagged_pattern()

frontends/systemverilog/uhdm_ast.h

@@ -208,6 +208,7 @@ class UhdmAst
     static const ::Yosys::IdString &is_simplified_wire();
     static const ::Yosys::IdString &low_high_bound();
     static const ::Yosys::IdString &is_elaborated_module();
+    static const ::Yosys::IdString &expand_genblock();
 };
 
 // Utility for building AstNode trees.

tests/formal/passlist.txt

@@ -82,6 +82,7 @@ simple:EnumBases/top.sv
 simple:EnumConcat/dut.v
 simple:EnumConcatenatedConst/top.sv
 simple:EnumConstX/top.sv
+simple:EnumInGenblock/top.sv
 simple:EnumInPackage/dut.sv
 simple:EnumItemReimport/top.sv
 simple:EnumParameterInNestedModules/top.sv
@@ -91,7 +92,6 @@ simple:event_implicit_expression_list/event_implicit.sv
 simple:ExpressionInIndex/top.sv
 simple:FileLevelParameter/top.sv
 simple:FileLevelUnionWithMultirange/top.sv
-simple:fsm_single_always/dut.v
 simple:fsm_using_always/dut.v
 simple:fsm_using_function/dut.v
 simple:Function2Returns/top.sv
@@ -155,6 +155,7 @@ simple:NestedParamSubstitution/top.sv
 simple:NestedSelectOnInputPortInGenscope/top.sv
 simple:NestedSelectOnVarInGenscope/top.sv
 simple:NestedStructArrayParameterInitializedByPatternPassedAsPort/top.sv
+simple:NestedStructs/top.sv
 simple:NoEdge/dut.sv
 simple:NoLatch/dut.sv
 simple:OneAlwaysComb/dut.v
@@ -172,6 +173,7 @@ simple:PackageEnumConstPush/dut.sv
 simple:PackageLogicTypespec/dut.sv
 simple:PackedArray/top.sv
 simple:PackedArrayPort/top.sv
+simple:PackedInGenblock/top.sv
 simple:ParameterColonReference/top.sv
 simple:ParameterConditionalAssignment/top.sv
 simple:ParameterDoubleUnderscoreInSvFrontend/my_pkg.sv
@@ -336,7 +338,6 @@ sv2v:core/enum_typedef_keep.sv
 sv2v:core/enum_typedef_keep.v
 sv2v:core/for_loop_inits.v
 sv2v:core/function_range_cast.v
-sv2v:core/function_ret_unpacked.v
 sv2v:core/function_void.v
 sv2v:core/func_no_asgn.sv
 sv2v:core/func_no_asgn.v
@@ -598,7 +599,6 @@ yosys:asicworld/code_tidbits_asyn_reset.v
 yosys:asicworld/code_tidbits_blocking.v
 yosys:asicworld/code_tidbits_fsm_using_always.v
 yosys:asicworld/code_tidbits_fsm_using_function.v
-yosys:asicworld/code_tidbits_fsm_using_single_always.v
 yosys:asicworld/code_tidbits_nonblocking.v
 yosys:asicworld/code_tidbits_reg_combo_example.v
 yosys:asicworld/code_tidbits_reg_seq_example.v
@@ -632,7 +632,6 @@ yosys:bind/cell_list.sv
 yosys:bind/inst_list.sv
 yosys:errors/syntax_err09.v
 yosys:errors/syntax_err13.v
-yosys:fmt/always_comb.v
 yosys:hana/test_parser.v
 yosys:hana/test_simulation_and.v
 yosys:hana/test_simulation_decoder.v
@@ -641,7 +640,6 @@ yosys:memlib/memlib_clock_sdp.v
 yosys:memlib/memlib_lut.v
 yosys:memlib/memlib_multilut.v
 yosys:memlib/memlib_wide_read.v
-yosys:memlib/memlib_wide_sdp.v
 yosys:memlib/memlib_wide_sp.v
 yosys:memlib/memlib_wide_write.v
 yosys:memories/firrtl_938.v
@@ -664,11 +662,8 @@ yosys:memories/wide_write.v
 yosys:opt/opt_rmdff_sat.v
 yosys:opt/opt_share_diff_port_widths.v
 yosys:opt/opt_share_extend.v
-yosys:opt/opt_share_large_pmux_cat.v
 yosys:opt/opt_share_large_pmux_cat_multipart.v
 yosys:opt/opt_share_large_pmux_multipart.v
-yosys:opt/opt_share_large_pmux_part.v
-yosys:opt/opt_share_mux_tree.v
 yosys:proc/bug_1268.v
 yosys:proc/rmdead.v
 yosys:sat/alu.v
@@ -735,7 +730,6 @@ yosys:simple/loop_var_shadow.v
 yosys:simple/macros.v
 yosys:simple/macro_arg_surrounding_spaces.v
 yosys:simple/matching_end_labels.sv
-yosys:simple/mem2reg_bounds_tern.v
 yosys:simple/memwr_port_connection.sv
 yosys:simple/mem_arst.v
 yosys:simple/module_scope.v
@@ -751,6 +745,7 @@ yosys:simple/retime.v
 yosys:simple/rotate.v
 yosys:simple/scopes.v
 yosys:simple/signedexpr.v
+yosys:simple/sign_part_assign.v
 yosys:simple/specify.v
 yosys:simple/string_format.v
 yosys:simple/subbytes.v
@@ -778,8 +773,8 @@ yosys:various/attrib07_func_call.v
 yosys:various/constmsk_test.v
 yosys:various/const_func_block_var.v
 yosys:various/countbits.sv
-yosys:various/dynamic_part_select/forloop_select.v
 yosys:various/dynamic_part_select/forloop_select_gate.v
+yosys:various/dynamic_part_select/forloop_select_nowrshmsk.v
 yosys:various/dynamic_part_select/latch_002.v
 yosys:various/dynamic_part_select/latch_002_gate.v
 yosys:various/dynamic_part_select/latch_002_gate_good.v
@@ -794,11 +789,9 @@ yosys:various/dynamic_part_select/original_gate.v
 yosys:various/dynamic_part_select/reset_test.v
 yosys:various/dynamic_part_select/reset_test_gate.v
 yosys:various/dynamic_part_select/reversed_gate.v
-yosys:various/elab_sys_tasks.sv
 yosys:various/gen_if_null.v
 yosys:various/pmux2shiftx.v
 yosys:various/reg_wire_error.sv
-yosys:various/smtlib2_module.v
 yosys:various/sub.v
 yosys:verific/case.sv
 yosys:verilog/bug656.v

tests/formal/skiplist.txt

@@ -53,12 +53,22 @@
 # This test sometimes fails due to how yosys assigns
 # wires to cells and the fact, that currently formal verification
 # requires the same order of assignments
+simple:fsm_single_always/dut.v
+yosys:simple/fsm.v
+yosys:fmt/always_comb.v
 yosys:opt/opt_lut.v
 yosys:simple/always03.v
 yosys:simple/operators.v
 yosys:asicworld/code_verilog_tutorial_fsm_full.v
 yosys:asicworld/code_hdl_models_GrayCounter.v
 yosys:simple/sincos.v
+yosys:asicworld/code_tidbits_fsm_using_single_always.v
+yosys:opt/opt_share_large_pmux_cat.v
+yosys:opt/opt_share_large_pmux_part.v
+yosys:opt/opt_share_mux_tree.v
+yosys:simple/mem2reg_bounds_tern.v
+yosys:various/elab_sys_tasks.sv
+yosys:various/smtlib2_module.v
 ########################################################################################
 # Type parameters in top modules cause the modules to be renamed
 # and handled incorrectly in verification scripts.

tests/simple_tests/EnumInGenblock/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/top.sv
+TOP_MODULE := top

tests/simple_tests/EnumInGenblock/top.sv

@@ -0,0 +1,31 @@
+module top();
+	if (1) begin : n
+		typedef enum logic [1:0] {
+			ALBL, ALBH, AHBL, AHBH
+		} mult_fsm_e;
+		mult_fsm_e mult_state_q, mult_state_d;
+
+		logic [1:0] a, b, c;
+
+		always_comb begin
+			unique case (mult_state_q)
+			ALBL: begin
+				a = 0;
+				c = ALBH;
+			end
+			ALBH: begin
+				a = 1;
+				c = AHBL;
+			end
+			AHBL: begin
+				a = 2;
+				c = AHBH;
+			end
+			AHBH: begin
+				a = 3;
+				c = ALBL;
+			end
+			endcase
+		end
+	end
+endmodule

tests/simple_tests/EnumInGenblock/yosys_script.tcl

@@ -0,0 +1,6 @@
+source ../yosys_common.tcl
+
+prep -top \\top
+write_verilog
+write_verilog yosys.sv
+sim -rstlen 10 -vcd dump.vcd

tests/simple_tests/GenblockAlwaysFor/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/top.sv
+TOP_MODULE := top

tests/simple_tests/GenblockAlwaysFor/top.sv

@@ -0,0 +1,41 @@
+typedef enum integer { pN = 0, pB = 1, pO = 2, pF = 3 } p_e;
+typedef enum logic [6:0] { ALU_N, ALU_B, ALU_H, ALU_BFP } op;
+module top #(parameter p_e p = pF) (input op i);
+	if (p != pN) begin : gen1
+		if (p == pO || p == pF) begin : gen2
+			logic  [7:0][2:0] sel_n;
+			logic  [3:0][1:0] sel_b;
+			logic  [1:0][0:0] sel_h;
+
+			logic [7:0][2:0] sel;
+
+			always_comb begin
+				unique case (i)
+					ALU_N: begin
+						sel = sel_n;
+					end
+
+					ALU_B: begin
+						for (int b = 0; b < 4; b++) begin
+							sel[b*2 +  0] =   {sel_b[b], 1'b0};
+							sel[b*2 +  1] =   {sel_b[b], 1'b1};
+						end
+					end
+
+					ALU_H: begin
+						for (int h = 0; h < 2; h++) begin
+							sel[h*4 +  0] =   {sel_h[h], 2'b00};
+							sel[h*4 +  1] =   {sel_h[h], 2'b01};
+							sel[h*4 +  2] =   {sel_h[h], 2'b10};
+							sel[h*4 +  3] =   {sel_h[h], 2'b11};
+						end
+					end
+
+					default: begin
+						sel = sel_n;
+					end
+				endcase
+			end
+		end
+	end
+endmodule

tests/simple_tests/GenblockAlwaysFor/yosys_script.tcl

@@ -0,0 +1,13 @@
+source ../yosys_common.tcl
+
+proc_clean
+proc_rmdead
+proc_prune
+proc_init
+proc_arst
+proc_mux
+proc_dff
+proc_clean
+proc_dlatch
+opt
+sim -rstlen 10 -vcd dump.vcd

tests/simple_tests/GenblockPackedAccess/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/top.sv
+TOP_MODULE := top

tests/simple_tests/GenblockPackedAccess/top.sv

@@ -0,0 +1,13 @@
+module top();
+	if (1) begin : n
+		typedef struct packed {
+			struct packed {
+				logic a;
+				logic b;
+			} foo;
+		} bar;
+		bar x;
+	end
+	assign n.x.foo.a = 0;
+	assign n.x.foo.b = 0;
+endmodule

tests/simple_tests/GenblockPackedAccess/yosys_script.tcl

@@ -0,0 +1,6 @@
+source ../yosys_common.tcl
+
+prep -top \\top
+write_verilog
+write_verilog yosys.sv
+sim -rstlen 10 -vcd dump.vcd

tests/simple_tests/MultipleNestedStructs/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/top.sv
+TOP_MODULE := top