Releases: chipsalliance/synlig
2023-10-03-fa53ffb: #2035: Fix plugin for Debian & test current release with `tuttest`
Fixes the plugin for Debian-packaged Yosys (this patch is needed for plugins loaded with that version).
Adds a test that installs the current release using the steps from the README.
Merges the tuttest
workflow into the main
workflow, as there is no clear split between those anymore.
2023-10-03-ca368ef: #2037: Build(deps): Bump third_party/OpenROAD-flow-scripts from `3c48244` to `8d866fc`
Bumps third_party/OpenROAD-flow-scripts from 3c48244
to 8d866fc
.
Commits
8d866fc
Merge pull request #1518 from The-OpenROAD-Project-staging/asap7-dbl-heightaea738a
Add double height 2-bit non-scan flops for asap7 from Dooseok Yoon0deb151
Merge pull request #1514 from The-OpenROAD-Project-staging/update-or96b284c
ci: update failing rules with new OR94c3eb7
Bump OR submodulea8ff675
Merge pull request #1508 from eder-matheus/update_asap7_mock_alu_metrics370357f
update asap7/mock-alu metrics and rulesb550767
Merge pull request #1506 from vvbandeira/bump-orab65d18
Bump OR submodule275b331
Merge pull request #1504 from vvbandeira/env-bash- Additional commits viewable in compare view
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2023-10-02-bb5d911: #2034: Fix unresolved `RTLIL::ID` symbols in old Yosys
Every so often, Yosys adds new vars in RTLIL::ID
. If the plugin is built with a newer version of Yosys that defines these new vars, but then loaded with an older one that doesn't, there's a symbol resolution error. This patch defines these vars in the plugin as well, as they're really just constants, so there's no issue in duplicating them.
2023-09-30-d3294c7: #2008: Bump Yosys
This bumps Yosys solving the issue with recent changes in the mainline: #1961
I've adjusted the references to Yosys' functions so that the plugin compiles.
There are Parsing Tests in Synlig which run simulation. Right now Yosys fails simulation if there are blackboxes. In such cases we should get rid of the simulation part.
Some tests are added to the skiplist as Yosys is unable to produce results that would be used in the Formal Verification tests.
2023-09-29-f12dffa: #2030: Custom edif backend
This allows us to use latest yosys. The upstream edif pass introduced
changes which are incompatible with SystemVerilog.
This should unblock #2008
2023-09-27-eb753f9: #2016: Fix path to formal verification README in summary
Currently the path is incorrect and clicking it results in a 404.
2023-09-27-e14de9e: #2017: bit select and range const push
Bump Surelog (#2017)
2023-09-27-bd35861: #2013: Add synthesis flow for Black Parrot design on ASIC PDK
This PR adds a synthesis flow for BlackParrot multicore design. It uses OpenROAD flow scripts and targets Nangate45 PDK but should be easily extendable to more platforms.
2023-09-26-af86685: #2012: Do not pull non-essential submodules by default.
Only yosys and surelog submodules are needed for plugin build. Those two are automatically fetched as before, i.e. after calling just git submodule update --recursive
.
All other submodules are skipped, even when their paths are explicitly specified. To fetch them one has to add --checkout
flag has to git submodule update
, e.g.:
git submodule update --dept 1 --init --recursive --checkout
Fixes #1962
2023-09-26-2224605: #1992: Fix enum item redeclaration error on reimport
Fixes #1988.
The error is caused by the enum being added during the iteration of the design, and then again during the iteration of uhdmtopModules
. Because the original enum is added at the top level, we don't see it so we add it again to individual modules.
Instead of adding typedefs at the top level, this patch makes it so we add it to each top module. Same thing with top-level parameters, as they may require these typedefs.