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@chriso
chriso committed Feb 27, 2022
1 parent 138e4a0 commit 955b003
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Showing 5 changed files with 125 additions and 6 deletions.
60 changes: 58 additions & 2 deletions decode.go
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Original file line number Diff line number Diff line change
Expand Up @@ -1652,10 +1652,12 @@ func decode_sve_sve_alloca(ins uint32, d *decoded) (err error) {
switch {
case op0 == 0x0 && op1 == 0x0:
err = decode_sve_sve_alloca_sve_int_arith_vl(ins, d)
case op0 == 0x0 && op1 == 0x1:
err = decode_sve_sve_alloca_sve_int_arith_svl(ins, d)
case op0 == 0x1 && op1 == 0x0:
err = decode_sve_sve_alloca_sve_int_read_vl_a(ins, d)
case op1 == 0x1:
err = errUnallocated
case op0 == 0x1 && op1 == 0x1:
err = decode_sve_sve_alloca_sve_int_read_svl_a(ins, d)
default:
err = errUnmatched
}
Expand All @@ -1680,6 +1682,24 @@ func decode_sve_sve_alloca_sve_int_arith_vl(ins uint32, d *decoded) (err error)
return
}

func decode_sve_sve_alloca_sve_int_arith_svl(ins uint32, d *decoded) (err error) {
d.iclass = iclass_sve_int_arith_svl
d.op = (ins >> 22) & 0x1
d.Rn = (ins >> 16) & 0x1f
d.imm6 = (ins >> 5) & 0x3f
d.Rd = (ins >> 0) & 0x1f

switch {
case d.op == 0x0:
d.encoding = encoding_addsvl_r_ri_
case d.op == 0x1:
d.encoding = encoding_addspl_r_ri_
default:
err = errUnmatched
}
return
}

func decode_sve_sve_alloca_sve_int_read_vl_a(ins uint32, d *decoded) (err error) {
d.iclass = iclass_sve_int_read_vl_a
d.op = (ins >> 22) & 0x1
Expand Down Expand Up @@ -1708,6 +1728,34 @@ func decode_sve_sve_alloca_sve_int_read_vl_a(ins uint32, d *decoded) (err error)
return
}

func decode_sve_sve_alloca_sve_int_read_svl_a(ins uint32, d *decoded) (err error) {
d.iclass = iclass_sve_int_read_svl_a
d.op = (ins >> 22) & 0x1
d.opc2 = (ins >> 16) & 0x1f
d.imm6 = (ins >> 5) & 0x3f
d.Rd = (ins >> 0) & 0x1f

switch {
case d.op == 0x0 && (d.opc2&0x10) == 0x0:
err = errUnallocated
case d.op == 0x0 && (d.opc2&0x18) == 0x10:
err = errUnallocated
case d.op == 0x0 && (d.opc2&0x1c) == 0x18:
err = errUnallocated
case d.op == 0x0 && (d.opc2&0x1e) == 0x1c:
err = errUnallocated
case d.op == 0x0 && d.opc2 == 0x1e:
err = errUnallocated
case d.op == 0x0 && d.opc2 == 0x1f:
d.encoding = encoding_rdsvl_r_i_
case d.op == 0x1:
err = errUnallocated
default:
err = errUnmatched
}
return
}

func decode_sve_sve_int_unpred_arit_b(ins uint32, d *decoded) (err error) {
op0 := (ins >> 11) & 0x3

Expand Down Expand Up @@ -8639,10 +8687,18 @@ func decode_control_branch_reg(ins uint32, d *decoded) (err error) {
err = errUnallocated
case d.opc == 0x2 && d.op2 == 0x1f && d.op3 == 0x2 && d.Rn != 0x1f && d.op4 != 0x1f:
err = errUnallocated
case d.opc == 0x2 && d.op2 == 0x1f && d.op3 == 0x2 && d.Rn != 0x1f && d.op4 == 0x1f:
err = errUnallocated
case d.opc == 0x2 && d.op2 == 0x1f && d.op3 == 0x2 && d.Rn == 0x1f && d.op4 != 0x1f:
err = errUnallocated
case d.opc == 0x2 && d.op2 == 0x1f && d.op3 == 0x2 && d.Rn == 0x1f && d.op4 == 0x1f:
d.encoding = encoding_RETAA_64E_branch_reg
case d.opc == 0x2 && d.op2 == 0x1f && d.op3 == 0x3 && d.Rn != 0x1f && d.op4 != 0x1f:
err = errUnallocated
case d.opc == 0x2 && d.op2 == 0x1f && d.op3 == 0x3 && d.Rn != 0x1f && d.op4 == 0x1f:
err = errUnallocated
case d.opc == 0x2 && d.op2 == 0x1f && d.op3 == 0x3 && d.Rn == 0x1f && d.op4 != 0x1f:
err = errUnallocated
case d.opc == 0x2 && d.op2 == 0x1f && d.op3 == 0x3 && d.Rn == 0x1f && d.op4 == 0x1f:
d.encoding = encoding_RETAB_64E_branch_reg
case d.opc == 0x2 && d.op2 == 0x1f && (d.op3&0x3c) == 0x4:
Expand Down
54 changes: 54 additions & 0 deletions encode.go
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Original file line number Diff line number Diff line change
Expand Up @@ -892,6 +892,24 @@ func encode_sve_int_arith_vl(op, Rn, imm6, Rd uint32) (ins uint32, err error) {
return
}

func encode_sve_int_arith_svl(op, Rn, imm6, Rd uint32) (ins uint32, err error) {
switch {
case op > 0x1 || Rn > 0x1f || imm6 > 0x3f || Rd > 0x1f:
err = errOverflow
case op == 0x0:
// encoding_addsvl_r_ri_
case op == 0x1:
// encoding_addspl_r_ri_
default:
err = errUnmatched
}

ins |= (op << 22) | (Rn << 16) | (imm6 << 5) | Rd
ins |= 0x4205800

return
}

func encode_sve_int_read_vl_a(op, opc2, imm6, Rd uint32) (ins uint32, err error) {
switch {
case op > 0x1 || opc2 > 0x1f || imm6 > 0x3f || Rd > 0x1f:
Expand Down Expand Up @@ -920,6 +938,34 @@ func encode_sve_int_read_vl_a(op, opc2, imm6, Rd uint32) (ins uint32, err error)
return
}

func encode_sve_int_read_svl_a(op, opc2, imm6, Rd uint32) (ins uint32, err error) {
switch {
case op > 0x1 || opc2 > 0x1f || imm6 > 0x3f || Rd > 0x1f:
err = errOverflow
case op == 0x0 && (opc2&0x10) == 0x0:
err = errUnallocated
case op == 0x0 && (opc2&0x18) == 0x10:
err = errUnallocated
case op == 0x0 && (opc2&0x1c) == 0x18:
err = errUnallocated
case op == 0x0 && (opc2&0x1e) == 0x1c:
err = errUnallocated
case op == 0x0 && opc2 == 0x1e:
err = errUnallocated
case op == 0x0 && opc2 == 0x1f:
// encoding_rdsvl_r_i_
case op == 0x1:
err = errUnallocated
default:
err = errUnmatched
}

ins |= (op << 22) | (opc2 << 16) | (imm6 << 5) | Rd
ins |= 0x4a05800

return
}

func encode_sve_int_mul_b(size, Zm, opc, Zn, Zd uint32) (ins uint32, err error) {
switch {
case size > 0x3 || Zm > 0x1f || opc > 0x3 || Zn > 0x1f || Zd > 0x1f:
Expand Down Expand Up @@ -6514,10 +6560,18 @@ func encode_branch_reg(opc, op2, op3, Rn, op4 uint32) (ins uint32, err error) {
err = errUnallocated
case opc == 0x2 && op2 == 0x1f && op3 == 0x2 && Rn != 0x1f && op4 != 0x1f:
err = errUnallocated
case opc == 0x2 && op2 == 0x1f && op3 == 0x2 && Rn != 0x1f && op4 == 0x1f:
err = errUnallocated
case opc == 0x2 && op2 == 0x1f && op3 == 0x2 && Rn == 0x1f && op4 != 0x1f:
err = errUnallocated
case opc == 0x2 && op2 == 0x1f && op3 == 0x2 && Rn == 0x1f && op4 == 0x1f:
// encoding_RETAA_64E_branch_reg
case opc == 0x2 && op2 == 0x1f && op3 == 0x3 && Rn != 0x1f && op4 != 0x1f:
err = errUnallocated
case opc == 0x2 && op2 == 0x1f && op3 == 0x3 && Rn != 0x1f && op4 == 0x1f:
err = errUnallocated
case opc == 0x2 && op2 == 0x1f && op3 == 0x3 && Rn == 0x1f && op4 != 0x1f:
err = errUnallocated
case opc == 0x2 && op2 == 0x1f && op3 == 0x3 && Rn == 0x1f && op4 == 0x1f:
// encoding_RETAB_64E_branch_reg
case opc == 0x2 && op2 == 0x1f && (op3&0x3c) == 0x4:
Expand Down
2 changes: 1 addition & 1 deletion gen/Makefile
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
ARCH=A64
VERSION=v9
EDITION=2021-09
EDITION=2021-12

ISA=ISA_$(ARCH)_xml_$(VERSION)A-$(EDITION)
ARCHIVE=$(ISA).tar.gz
Expand Down
2 changes: 1 addition & 1 deletion gen/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -3,5 +3,5 @@ using the A64 ISA spec.

The input XML files are available at https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools

The generator has been tested with **Armv9-A 2021-09** only.
The generator has been tested with **Armv9-A 2021-12** only.

13 changes: 11 additions & 2 deletions iclass.go
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Original file line number Diff line number Diff line change
Expand Up @@ -79,8 +79,10 @@ const (
iclass_sve_int_index_rr // SVE index generation (register start, register increment)

// sve > sve_alloca
iclass_sve_int_arith_vl // SVE stack frame adjustment
iclass_sve_int_read_vl_a // SVE stack frame size
iclass_sve_int_arith_vl // SVE stack frame adjustment
iclass_sve_int_arith_svl // sve_int_arith_svl
iclass_sve_int_read_vl_a // SVE stack frame size
iclass_sve_int_read_svl_a // sve_int_read_svl_a

// sve > sve_int_unpred_arit_b
iclass_sve_int_mul_b // SVE2 integer multiply vectors (unpredicated)
Expand Down Expand Up @@ -738,9 +740,16 @@ const (
encoding_addvl_r_ri_ // ADDVL
encoding_addpl_r_ri_ // ADDPL

// iclass_sve_int_arith_svl
encoding_addsvl_r_ri_ // ADDSVL
encoding_addspl_r_ri_ // ADDSPL

// iclass_sve_int_read_vl_a
encoding_rdvl_r_i_ // RDVL

// iclass_sve_int_read_svl_a
encoding_rdsvl_r_i_ // RDSVL

// iclass_sve_int_mul_b
encoding_mul_z_zz_ // MUL (vectors, unpredicated)
encoding_smulh_z_zz_ // SMULH (unpredicated)
Expand Down

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