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Optimise reset insertion for mapped gates
Closes workcraft#1649
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,14 +1,14 @@ | ||
Initialisation check: true | ||
Combined check: true | ||
Circuit analysis: | ||
Component count (mapped + unmapped) - 16 (16 + 0) | ||
Area - 176.0 + C2R | ||
Non-trivial component count (function + blackbox) - 8 (8 + 0) | ||
Component count (mapped + unmapped) - 15 (15 + 0) | ||
Area - 164.0 + C2R | ||
Non-trivial component count (function + blackbox) - 7 (7 + 0) | ||
Trivial gate count (buffer / 0-delay + inverter / 0-delay + const) - 8 (2 / 0 + 6 / 5 + 0) | ||
Driver pin count (combinational + sequential + undefined) - 16 (15 + 1 + 0) | ||
Literal count combinational / sequential (set + reset) - 30 / 6 (3 + 3) | ||
Driver pin count (combinational + sequential + undefined) - 15 (14 + 1 + 0) | ||
Literal count combinational / sequential (set + reset) - 29 / 6 (3 + 3) | ||
Port count (input + output) - 11 (6 + 5) | ||
Max fanin / fanout - 4 / 4 | ||
Fanin distribution [0 / 1 / 2 ...] - 0 / 8 / 3 / 1 / 4 | ||
Fanout distribution [0 / 1 / 2 ...] - 0 / 11 / 8 / 1 / 2 | ||
Max fanin / fanout - 5 / 4 | ||
Fanin distribution [0 / 1 / 2 ...] - 0 / 8 / 2 / 1 / 3 / 1 | ||
Fanout distribution [0 / 1 / 2 ...] - 0 / 10 / 8 / 1 / 2 | ||
Isolated components / ports / pins - 0 / 0 / 0 |
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