add some documentation

docs/api/configuration.rst

@@ -70,6 +70,7 @@ It looks like this:
    OutputPredictions: keras/KERAS_3layer_predictions.dat
 
    # Backend section (Vivado backend)
+   Backend: Vivado
    Part: xcvu13p-flga2577-2-e
    ClockPeriod: 5
    IOType: io_parallel # options: io_parallel/io_stream
@@ -107,6 +108,28 @@ For Vivado backend the options are:
   * **Precision**\ : this defines the precsion of your inputs, outputs, weights and biases. It is denoted by ``ap_fixed<X,Y>``\ , where ``Y`` is the number of bits representing the signed number above the binary point (i.e. the integer part), and ``X`` is the total number of bits.
   Additionally, integers in fixed precision data type (\ ``ap_int<N>``\ , where ``N`` is a bit-size from 1 to 1024) can also be used. You have a chance to further configure this more finely with per-layer configuration described below.
 
+The Catapult backend also provides these options:
+* **Technology**\ : specifies either 'fpga' or 'asic'
+* **ASICLibs**\ : the list of ASIC libraries to load, for example: saed32rvt_tt0p78v125c_beh
+* **FIFO**\ : specifies the name of the FIFO interconnect component to use
+
+In addition to the new configuration options, the Catapult backend build() method has the following additional switches:
+.. code-block:: python
+
+   hls_model.build(csim=True,synth=True,cosim=False,vhdl=False,verilog=True,ran_frame=5,sw_opt=False,power=False,da=False,bup=False)
+   where:
+      csim - run C++ model execution
+      synth - perform Catapult HLS synthesis
+      cosim - enable SCVerify C-vs-RTL verification after HLS is done
+      vhdl  - enable VHDL RTL netlist generation
+      verilog - enable Verilog RTL netlist generation
+      ran_frame - if no InputData and OutputPredictions provided, simulate the network with random feature data for ran_frame frames
+      sw_opt - run power estimation on the pre-power RTL netlist
+      power - run Catapult Power Optimization on the RTL
+      da - invoke Catapult Design Analyzer
+      bup - perform HLS in a bottom-up fashion
+
+
 2.2 Per-Layer Configuration
 ---------------------------
 

docs/details.rst

@@ -7,7 +7,7 @@ Frontends and Backends
 
 In ``hls4ml`` there is a a concept of a *frontend* to parse the input NN into an internal model graph, and a *backend* that controls
 what type of output is produced from the graph. Frontends and backends can be independently chosen. Examples of frontends are the
-parsers for Keras or ONNX, and examples of backends are Vivado HLS, Intel HLS, and Vitis HLS. See :ref:`Status and Features` for the
+parsers for Keras or ONNX, and examples of backends are Vivado HLS, Intel HLS, Catapult HLS, and Vitis HLS. See :ref:`Status and Features` for the
 currently supported frontends and backends.
 
 I/O Types

docs/status.rst

@@ -32,6 +32,7 @@ HLS backends:
 
 * Vivado HLS
 * Intel HLS
+* Catapult HLS (beta)
 * Vitis HLS (experimental)
 
 A summary of the on-going status of the ``hls4ml`` tool is in the table below.
@@ -45,27 +46,31 @@ A summary of the on-going status of the ``hls4ml`` tool is in the table below.
      - (Q)ONNX
      - Vivado HLS
      - Intel HLS
+     - Catapult HLS
      - Vitis HLS
    * - MLP
      - ``supported``
      - ``limited``
      - ``in development``
      - ``supported``
      - ``supported``
+     - ``supported``
      - ``experimental``
    * - CNN
      - ``supported``
      - ``limited``
      - ``in development``
      - ``supported``
      - ``supported``
+     - ``supported``
      - ``experimental``
    * - RNN (LSTM)
      - ``supported``
      - ``N/A``
      - ``in development``
      - ``supported``
      - ``supported``
+     - ``supported``
      - ``N/A``
    * - GNN (GarNet)
      - ``supported``
@@ -74,13 +79,15 @@ A summary of the on-going status of the ``hls4ml`` tool is in the table below.
      - ``N/A``
      - ``N/A``
      - ``N/A``
+     - ``N/A``
 
 
 Other feature notes:
 
 * ``hls4ml`` is tested on Linux, and supports
    * Vivado HLS versions 2018.2 to 2020.1
    * Intel HLS versions 20.1 to 21.4
+   * Catapult HLS versions 2024.1 (beta)
    * Vitis HLS versions 2020.2 to 2022.2 (experimentally)
 * Windows and macOS are not supported
 * BDT support has moved to the `Conifer <https://github.com/thesps/conifer>`__ package

hls4ml/backends/catapult/catapult_backend.py

@@ -207,7 +207,8 @@ def build(
         ran_frame=5,
         sw_opt=False,
         power=False,
-        da=False
+        da=False,
+        bup=False
     ):
         # print(f'ran_frame value: {ran_frame}')  # Add this line for debugging
         catapult_exe = 'catapult'
@@ -226,7 +227,7 @@ def build(
 
         curr_dir = os.getcwd()
         os.chdir(model.config.get_output_dir())
-        ccs_args = '"reset={reset} csim={csim} synth={synth} cosim={cosim} validation={validation} export={export} vsynth={vsynth} fifo_opt={fifo_opt} bitfile={bitfile} ran_frame={ran_frame} sw_opt={sw_opt} power={power} da={da} vhdl={vhdl} verilog={verilog}"'.format(reset=reset, csim=csim, synth=synth, cosim=cosim, validation=validation, export=export, vsynth=vsynth, fifo_opt=fifo_opt, bitfile=bitfile, ran_frame=ran_frame, sw_opt=sw_opt, power=power, da=da, vhdl=vhdl, verilog=verilog)
+        ccs_args = '"reset={reset} csim={csim} synth={synth} cosim={cosim} validation={validation} export={export} vsynth={vsynth} fifo_opt={fifo_opt} bitfile={bitfile} ran_frame={ran_frame} sw_opt={sw_opt} power={power} da={da} vhdl={vhdl} verilog={verilog} bup={bup}"'.format(reset=reset, csim=csim, synth=synth, cosim=cosim, validation=validation, export=export, vsynth=vsynth, fifo_opt=fifo_opt, bitfile=bitfile, ran_frame=ran_frame, sw_opt=sw_opt, power=power, da=da, vhdl=vhdl, verilog=verilog, bup=bup)
         ccs_invoke = catapult_exe + ' -product ultra -shell -f build_prj.tcl -eval \'set ::argv ' + ccs_args + '\''
         print(ccs_invoke)
         os.system(ccs_invoke)