For in-depth end-to-end instructions check our tutorials.
For reference documentation see our website.
- Pull and run Tensil docker container (see below);
- Download and install Xilinx Vitis or Vivado;
- Download and install Xilinx PYNQ for your FPGA development platform;
- Copy Tensil PYNQ driver
drivers/tcu_pynq
to/home/xilinx/tcu_pynq
on your FPGA development platform.
docker pull tensilai/tensil
docker run -v $(pwd):/work -w /work -it tensilai/tensil bash
Compile AI/ML model (ResNet20 v2 CIFAR) for specific TCU architecture and FPGA development platform, PYNQ Z1 in this example.
tensil compile -a /demo/arch/pynqz1.tarch -m /demo/models/resnet20v2_cifar.onnx -o "Identity:0" -s true
tensil compile -a /demo/arch/pynqz1.tarch -m /demo/models/resnet20v2_cifar.pb -o "Identity" -s true
Make Verilog RTL for specific TCU architecture and FPGA development platform, PYNQ Z1 in this example.
tensil rtl -a /demo/arch/pynqz1.tarch -s true
Create Vivado design for specific FPGA development platform. We include detailed steps in our PYNQ Z1 tutorial. If you get stuck, we can help! Please reach out to us at [email protected] or in Discord.
Use PYNQ and Jupyter notebooks to run AI/ML model on FPGA. (See in notebooks
.)
- Download and install OpenJDK 11 from Azul;
- Download and install Verilator;
- Download test models:
wget https://github.com/tensil-ai/tensil-models/archive/main.tar.gz
tar xf main.tar.gz
mv tensil-models-main models
rm main.tar.gz
./mill rtl.run -a ./arch/pynqz1.tarch -s true
./mill tools.run -a ./arch/pynqz1.tarch -m ./models/resnet20v2_cifar.onnx -o "Identity:0" -s true
./mill __.test -l org.scalatest.tags.Slow
- Say hello and ask a question on our Discord
- Email us at [email protected]