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more spibuffer
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@dheijl
dheijl committed Jan 19, 2025
1 parent a437cec commit 30bb53e
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Showing 3 changed files with 53 additions and 35 deletions.
4 changes: 2 additions & 2 deletions echo_spi_clkwiz/source/spi_echo.luc
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ module spi_echo (
SPI Mode 2 = CPOL 1 CPHA 0
SPI Mode 3 = CPOL 1 CPHA 1
*/

.clk(fst_clk) {
.rst(rst) {
spi_peripheral spi (#CPOL(0), #CPHA(1),
Expand Down Expand Up @@ -53,11 +53,11 @@ module spi_echo (

// sync the 200 MHz fifo with the 100 MHz output
if (clock_syncer.q == 2b01) {
clock_syncer.d = 2b00
if (! fifo_out.empty) {
out_buf.d = fifo_out.dout
rdy.d = 1b1
fifo_out.rget = 1b1
clock_syncer.d = 2b00
}
} else {
rdy.d = 1b0
Expand Down
38 changes: 19 additions & 19 deletions teensy_spi_clkwiz/source/alchitry_top.luc
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ module alchitry_top (
input sdi, // spi mosi
input cs, // spi slave select
output sdo, // spi miso
output drq // spi data transfer request
output drq // SPI transfer request
) {

sig rst // reset signal
Expand All @@ -26,23 +26,21 @@ module alchitry_top (

clk_wiz_0 clkwiz(.clk_in1(clk), .reset(rst))

spi_buffer spibuffer(
spi_buffer spibuffer(#BUFFER_SIZE(256),
.fst_clk(clkwiz.clk_out2),
.rst(rst),
.sck(sck),
.sdi(sdi),
.cs(cs)
)


)

always {
reset_cond.in = ~rst_n // input raw inverted reset signal
rst = reset_cond.out // conditioned reset

// connect spi
sdo = spibuffer.sdo
drq = 1b0
drq = spibuffer.drq

// connect usb
tx.block = 1b0
Expand All @@ -62,27 +60,20 @@ module alchitry_top (
// leds
led[0] = echo.empty
led[1] = echo.full
led[2] = 1b0
led[3] = 1b0
led[4] = 1b0
led[2] = spibuffer.data_rdy
led[3] = spibuffer.data_in_full
led[4] = spibuffer.drq
led[5] = 1b0
led[6] = sck
led[7] = ~cs

// put received SPI characters in console echo buffer
if (spibuffer.data_rdy && !echo.full) {
echo.din = spibuffer.data_out
echo.wput = 1b1
}
// echo eceived characters (spi or console) to console
if (!echo.empty && !tx.busy ) {
tx.data = echo.dout
tx.new_data = 1b1
echo.rget = 1b1
} else {
tx.data = 1b0
tx.new_data = 1b0
}

// put received console characters in console echo buffer
// and in SPI transmit buffer
if (rx.new_data && !echo.full) {
echo.din = rx.data
echo.wput = 1b1
Expand All @@ -91,5 +82,14 @@ module alchitry_top (
spibuffer.data_in_newdata = 1b1
}
}
// echo received characters (spi or console) to console
if (!echo.empty && !tx.busy ) {
tx.data = echo.dout
tx.new_data = 1b1
echo.rget = 1b1
} else {
tx.data = 1b0
tx.new_data = 1b0
}
}
}
46 changes: 32 additions & 14 deletions teensy_spi_clkwiz/source/spi_buffer.luc
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
module spi_buffer (
module spi_buffer #(BUFFER_SIZE = 256)
(
input fst_clk, // 200 MHz clock
input rst, // reset
input sck, // spi clock
Expand All @@ -9,32 +10,37 @@ module spi_buffer (
output data_in_full, // space available in fifo_in
output sdo, // spi miso
output data_out[8], // received spi data from fifo_out
output data_rdy // spi rcv fifo not empty
output data_rdy, // spi rcv fifo not empty
output drq // request SPI transfer
) {
/*
SPI Mode 0 = CPOL 0 CPHA 0
SPI Mode 1 = CPOL 0 CPHA 1
SPI Mode 2 = CPOL 1 CPHA 0
SPI Mode 3 = CPOL 1 CPHA 1
*/

.clk(fst_clk) {
.rst(rst) {
spi_peripheral spi (#CPOL(0), #CPHA(1),
.cs(cs),
.sck(sck),
.sdi(sdi))

fifo fifo_out(#WIDTH(8), #ENTRIES(256))
fifo fifo_in(#WIDTH(8), #ENTRIES(256))
fifo fifo_out(#WIDTH(8), #ENTRIES(BUFFER_SIZE)) // SPI data received
fifo fifo_in(#WIDTH(8), #ENTRIES(BUFFER_SIZE)) // data to transmit
}
dff tx_buf[8] // the character to transmit
dff out_buf[8] // the received SPI character
dff tx_buf[8] // the SPI character to transmit
dff rx_buf[8] // the received SPI character
dff rdy // the SPI char ready flag
dff have_output
dff have_input
dff clock_syncer[2]
dff cs_reg
dff data_in_reg[8]
dff data_out_reg[8]
dff drq_reg
dff new_data_reg
}


Expand All @@ -55,28 +61,39 @@ module spi_buffer (
fifo_in.rget = 1b0

// drive outputs
data_out = out_buf.q
data_out = data_out_reg.q
data_rdy = rdy.q
data_in_full = fifo_in.full
drq = drq_reg.q
// inputs
new_data_reg.d = data_in_newdata
data_in_reg.d = data_in

// make sure the first byte is ready when SPI transfer starts
data_in_reg.d = data_in
if (! fifo_in.empty) {
if (! have_input.q && ! fifo_in.empty) {
tx_buf.d = fifo_in.dout
fifo_in.rget = 1b1
have_input.d = 1b1
}
if (fifo_in.empty) {
drq_reg.d = 1b0
}
spi.data_in = tx_buf.q

// sync the 200 MHz fifo with the 100 MHz output
if (clock_syncer.q == 2b01) {
if (! fifo_out.empty) {
out_buf.d = fifo_out.dout
data_out_reg.d = fifo_out.dout
rdy.d = 1b1
fifo_out.rget = 1b1
}
if (! fifo_in.full && data_in_newdata) {
if (! fifo_in.full && new_data_reg.q) {
fifo_in.din = data_in_reg.q
fifo_in.wput = 1b1
// trigger SPI transmission on newline or buffer full
if ((data_in_reg.q == 8h0a) || (fifo_in.full)) {
drq_reg.d = 1b1
}
}
clock_syncer.d = 2b00
} else {
Expand All @@ -87,7 +104,7 @@ module spi_buffer (
// store any received spi char in output fifo
if (have_output.q) {
if (!fifo_out.full) {
fifo_out.din = tx_buf.q
fifo_out.din = rx_buf.q
fifo_out.wput = 1b1
have_output.d = 1b0
}
Expand All @@ -98,10 +115,11 @@ module spi_buffer (
} else { // SPI active
if (spi.done) {
// echo received characters to SPI
tx_buf.d = spi.data_out
rx_buf.d = spi.data_out
spi.data_in = tx_buf.q
// output received spi char to the fifo
have_output.d = 1b1
have_input.d = 1b0
}
}
}
Expand Down

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