Skip to content

Commit

Permalink
cores
Browse files Browse the repository at this point in the history
  • Loading branch information
@dheijl
dheijl committed Feb 9, 2025
1 parent 5962ae8 commit 8a97511
Show file tree
Hide file tree
Showing 21 changed files with 4,663 additions and 4,663 deletions.
Binary file modified teensy_spi/cores/fifo_256/fifo_256.dcp
100644 → 100755
View file
Binary file not shown.
44 changes: 22 additions & 22 deletions teensy_spi/cores/fifo_256/fifo_256.xml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2338,7 +2338,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 08 16:21:33 UTC 2025</spirit:value>
<spirit:value>Sat Feb 08 16:51:47 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Expand All @@ -2356,11 +2356,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 08 16:21:34 UTC 2025</spirit:value>
<spirit:value>Sat Feb 08 16:51:47 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9cdc3550</spirit:value>
<spirit:value>9:0b6048d8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -2374,7 +2374,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 08 16:21:33 UTC 2025</spirit:value>
<spirit:value>Sat Feb 08 16:51:47 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Expand All @@ -2393,7 +2393,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 08 16:21:33 UTC 2025</spirit:value>
<spirit:value>Sat Feb 08 16:51:47 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Expand All @@ -2413,7 +2413,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 08 16:21:33 UTC 2025</spirit:value>
<spirit:value>Sat Feb 08 16:51:47 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Expand All @@ -2431,7 +2431,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 08 16:21:33 UTC 2025</spirit:value>
<spirit:value>Sat Feb 08 16:51:47 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Expand All @@ -2454,7 +2454,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 08 16:21:33 UTC 2025</spirit:value>
<spirit:value>Sat Feb 08 16:51:47 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Expand All @@ -2474,7 +2474,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 08 16:21:33 UTC 2025</spirit:value>
<spirit:value>Sat Feb 08 16:51:47 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Expand Down Expand Up @@ -9287,16 +9287,17 @@
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>fifo_256.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:name>fifo_256_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>fifo_256_stub.v</spirit:name>
<spirit:name>fifo_256_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
Expand All @@ -9306,17 +9307,16 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>fifo_256_sim_netlist.v</spirit:name>
<spirit:name>fifo_256_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>fifo_256_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:name>fifo_256.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
Expand Down
Loading

0 comments on commit 8a97511

Please sign in to comment.