Update Litex mgmt soc

.gitignore

@@ -1,5 +1,9 @@
+*.swp
+*.swo
 /.idea/
 /litex/build/
+/litex/env/
+/litex/__pycache__
 ./openlane/mgmt_core/runs/
 /openlane/mgmt_core_wrapper/runs/
 *.hex*

.gitmodules

@@ -0,0 +1,39 @@
+[submodule "litex/third_party/litex"]
+	path = litex/third_party/litex
+	url = https://github.com/enjoy-digital/litex.git
+[submodule "litex/third_party/litespi"]
+	path = litex/third_party/litespi
+	url = https://github.com/litex-hub/litespi.git
+[submodule "litex/third_party/pythondata-cpu-vexriscv"]
+	path = litex/third_party/pythondata-cpu-vexriscv
+	url = https://github.com/litex-hub/pythondata-cpu-vexriscv.git
+[submodule "litex/third_party/pythondata-software-picolibc"]
+	path = litex/third_party/pythondata-software-picolibc
+	url = https://github.com/litex-hub/pythondata-software-picolibc.git
+[submodule "litex/third_party/migen"]
+	path = litex/third_party/migen
+	url = http://github.com/m-labs/migen.git
+[submodule "litex/third_party/pythondata-cpu-picorv32"]
+	path = litex/third_party/pythondata-cpu-picorv32
+	url = https://github.com/litex-hub/pythondata-cpu-picorv32.git
+[submodule "litex/third_party/pythondata-cpu-ibex"]
+	path = litex/third_party/pythondata-cpu-ibex
+	url = https://github.com/litex-hub/pythondata-cpu-ibex.git
+[submodule "litex/third_party/litedram"]
+	path = litex/third_party/litedram
+	url = https://github.com/enjoy-digital/litedram
+[submodule "litex/third_party/liteeth"]
+	path = litex/third_party/liteeth
+	url = https://github.com/enjoy-digital/liteeth
+[submodule "litex/third_party/liteiclink"]
+	path = litex/third_party/liteiclink
+	url = https://github.com/enjoy-digital/liteiclink
+[submodule "litex/third_party/litescope"]
+	path = litex/third_party/litescope
+	url = https://github.com/enjoy-digital/litescope
+[submodule "litex/third_party/pythondata-misc-tapcfg"]
+	path = litex/third_party/pythondata-misc-tapcfg
+	url = https://github.com/litex-hub/pythondata-misc-tapcfg.git
+[submodule "litex/third_party/pythondata-software-compiler_rt"]
+	path = litex/third_party/pythondata-software-compiler_rt
+	url = https://github.com/litex-hub/pythondata-software-compiler_rt.git

Makefile

@@ -89,6 +89,10 @@ SKYWATER_COMMIT ?= c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
 OPEN_PDKS_COMMIT ?= de752ec0ba4da0ecb1fbcd309eeec4993d88f5bc
 INSTALL_SRAM ?= disabled
 
+#Generates the header files for the mgmt soc core
+generate_mgmt_soc_headers:
+	$(MAKE) -C litex $@
+
 .DEFAULT_GOAL := ship
 # We need portable GDS_FILE pointers...
 .PHONY: ship

litex/Makefile

@@ -13,16 +13,33 @@
 # limitations under the License.
 #
 # SPDX-License-Identifier: Apache-2.0
+PYTHON ?= python3
+IN_ENV = if [ -e env/bin/activate ]; then . env/bin/activate; fi;
+ROOT_DIR:=$(shell dirname $(realpath $(firstword $(MAKEFILE_LIST))))
+LITEX_BUILD_DIR = $(ROOT_DIR)/build/caravel_platform
+MGMT_SOC_DIR = $(ROOT_DIR)/../verilog
 
-all: mgmt_soc
+all: update_mgmt_soc_gateware generate_mgmt_soc_headers
 
-mgmt_soc: caravel.py
-	python3 caravel.py
-	python3 modify_verilog.py
-	cp build/caravel_platform/gateware/mgmt_core_modified.v ../verilog/rtl/mgmt_core.v
-	cp -R build/caravel_platform/software/include/generated ../verilog/dv/.
+update_mgmt_soc_gateware: $(MGMT_SOC_DIR)/rtl/mgmt_core.v
+generate_mgmt_soc_headers: $(MGMT_SOC_DIR)/dv/generated/variables.mak
 
-setup:
-	pip3 install -r requirements.txt
+$(MGMT_SOC_DIR)/rtl/mgmt_core.v: $(LITEX_BUILD_DIR)/gateware/mgmt_core.v
+	$(IN_ENV) python modify_verilog.py $< $@
 
-.PHONY: clean hex all
+$(MGMT_SOC_DIR)/dv/generated/variables.mak: $(LITEX_BUILD_DIR)/software/include/generated/variables.mak
+	cp -R $(LITEX_BUILD_DIR)/software/include/generated $(MGMT_SOC_DIR)/dv/.
+
+$(LITEX_BUILD_DIR)/gateware/mgmt_core.v $(LITEX_BUILD_DIR)/software/include/generated/variables.mak: caravel.py | env
+	$(IN_ENV) python caravel.py
+
+setup: env
+
+env:
+	@$(PYTHON) -mvenv env
+	@$(IN_ENV) pip3 install -r requirements.txt
+
+clean:
+	rm -rf build env __pycache__
+
+.PHONY: clean all

litex/caravel.py

@@ -10,21 +10,20 @@
 from os import path
 
 from migen import *
-from litex.soc.cores.spi_flash import SpiFlash
-from litex.soc.integration.soc_core import SoCCore
+from litex.soc.integration.soc_core import SoCMini
 from litex.soc.integration.builder import Builder, builder_argdict, builder_args
 from litex.soc.integration.soc_core import soc_core_argdict, soc_core_args
 from litex.soc.integration.doc import AutoDoc
 from litex.soc.integration.soc import SoCRegion, SoCIORegion
-from litex.soc.integration.soc_core import *
+#from litex.soc.integration.soc_core import *
 from litex.build.generic_platform import *
 from litex.soc.cores.uart import UARTWishboneBridge, UART, RS232PHY, UARTPHY
 from litex.soc.cores.gpio import *
 from caravel_gpio import *
 from litex.soc.cores.spi import SPIMaster, SPISlave
 import litex.soc.doc as lxsocdoc
 
-from caravel_platform import Platform
+from caravel_platform import CaravelPlatform
 from caravel_ram import *
 
 # SoCMini.mem_map = {
@@ -38,17 +37,16 @@
 
 # MGMTSoC
 class MGMTSoC(SoCMini):
-
-    def __init__(self, sys_clk_freq=int(10e6), **kwargs ):
+    def __init__(self, sys_clk_freq=int(10e6), platform_class=CaravelPlatform, cpu='vexriscv', **kwargs ):
 
         ##
         ## Uncomment cpu selection for mgmt core below
         ##
         # cpu = 'picorv32'
         # cpu = 'ibex'
-        cpu = 'vexriscv'
+        # cpu = 'vexriscv'
 
-        platform = Platform("mgmt_soc")
+        platform = platform_class("mgmt_soc")
 
         # CRG --------------------------------------------------------------------------------------
         # self.submodules.crg = CRG(platform.request("core_clk"), rst=platform.request("core_rst"))
@@ -145,7 +143,7 @@ def __init__(self, sys_clk_freq=int(10e6), **kwargs ):
         #DFFRAM
         dff_size = 1 * 1024
         dff = self.submodules.mem = DFFRAM(size=dff_size)
-        self.register_mem("dff", self.mem_map["dff"], self.mem.bus, dff_size)
+        self.bus.add_slave("dff", self.mem.bus, SoCRegion(origin=self.mem_map["dff"], size=dff_size))
         # mgmt_soc_dff = platform.request("mgmt_soc_dff")
         # self.comb += mgmt_soc_dff.WE.eq(dff.we)
         # self.comb += mgmt_soc_dff.A.eq(dff.bus.adr)
@@ -156,7 +154,7 @@ def __init__(self, sys_clk_freq=int(10e6), **kwargs ):
         #DFFRAM2
         dff2_size = 512
         dff2 = self.submodules.mem2 = DFFRAM_512(size=dff2_size)
-        self.register_mem("dff2", self.mem_map["dff2"], self.mem2.bus, dff2_size)
+        self.bus.add_slave("dff2", self.mem2.bus, SoCRegion(origin=self.mem_map["dff2"], size=dff2_size))
 
         # #OpenRAM
         # spram_size = 2 * 1024
@@ -219,7 +217,7 @@ def __init__(self, sys_clk_freq=int(10e6), **kwargs ):
         # Add Debug Interface (UART)
         dbg_uart = Record([('rx',1),('tx',1)])
         self.submodules.dbg_uart = UARTWishboneBridge(dbg_uart, sys_clk_freq, baudrate=115200)
-        self.add_wb_master(self.dbg_uart.wishbone)
+        self.bus.add_master(master=self.dbg_uart.wishbone)
 
         # Instantiate ports for debug & serial i/f
         uart_ports = platform.request("serial")
@@ -316,52 +314,59 @@ def __init__(self, sys_clk_freq=int(10e6), **kwargs ):
 
     #####################
 
-    def new_add_spi_flash(self, name="flash", mode="4x", dummy_cycles=None, clk_freq=None, module=None, phy=None, rate="1:1", **kwargs):
-        if module is None:
-            # Use previous LiteX SPI Flash core with compat, will be deprecated at some point.
-            from litex.compat.soc_add_spi_flash import add_spi_flash
-            add_spi_flash(self, name, mode, dummy_cycles)
-        # LiteSPI.
-        else:
-            # Imports.
-            from litespi import LiteSPI
-            # from litespi.phy.generic import LiteSPIPHY
-            from generic import LiteSPIPHY
-            from litespi.opcodes import SpiNorFlashOpCodes
-
-            # Checks/Parameters.
-            assert mode in ["1x", "4x"]
-            if clk_freq is None: clk_freq = self.sys_clk_freq
-
-            # PHY.
-            spiflash_phy = phy
-            if spiflash_phy is None:
-                self.check_if_exists(name + "_phy")
-                spiflash_pads = self.platform.request(name)
-                # spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
-                spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=int(self.sys_clk_freq/clk_freq), rate=rate)
-                setattr(self.submodules, name + "_phy",  spiflash_phy)
-
-            # Core.
-            self.check_if_exists(name + "_mmap")
-            spiflash_core = LiteSPI(spiflash_phy, mmap_endianness=self.cpu.endianness, **kwargs)
-            setattr(self.submodules, name + "_core", spiflash_core)
-            spiflash_region = SoCRegion(origin=self.mem_map.get(name, None), size=module.total_size)
-            self.bus.add_slave(name=name, slave=spiflash_core.bus, region=spiflash_region)
-
-            # Constants.
-            self.add_constant("SPIFLASH_PHY_FREQUENCY", clk_freq)
-            self.add_constant("SPIFLASH_MODULE_NAME", module.name.upper())
-            self.add_constant("SPIFLASH_MODULE_TOTAL_SIZE", module.total_size)
-            self.add_constant("SPIFLASH_MODULE_PAGE_SIZE", module.page_size)
-            if SpiNorFlashOpCodes.READ_1_1_4 in module.supported_opcodes:
-                self.add_constant("SPIFLASH_MODULE_QUAD_CAPABLE")
-            if SpiNorFlashOpCodes.READ_4_4_4 in module.supported_opcodes:
-                self.add_constant("SPIFLASH_MODULE_QPI_CAPABLE")
+    def new_add_spi_flash(self, name="flash", mode="4x", clk_freq=None, module=None, phy=None, rate="1:1", **kwargs):
+        # Imports.
+        from litespi import LiteSPI
+        # from litespi.phy.generic import LiteSPIPHY
+        from generic import LiteSPIPHY
+        from litespi.opcodes import SpiNorFlashOpCodes
+
+        # Checks/Parameters.
+        assert mode in ["1x", "4x"]
+        if clk_freq is None: clk_freq = self.sys_clk_freq
+
+        # PHY.
+        spiflash_phy = phy
+        if spiflash_phy is None:
+            self.check_if_exists(name + "_phy")
+            spiflash_pads = self.platform.request(name)
+            # spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
+            spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=int(self.sys_clk_freq/clk_freq), rate=rate)
+            setattr(self.submodules, name + "_phy",  spiflash_phy)
+
+        # Core.
+        self.check_if_exists(name + "_mmap")
+        spiflash_core = LiteSPI(spiflash_phy, mmap_endianness=self.cpu.endianness, **kwargs)
+        setattr(self.submodules, name + "_core", spiflash_core)
+        spiflash_region = SoCRegion(origin=self.mem_map.get(name, None), size=module.total_size)
+        self.bus.add_slave(name=name, slave=spiflash_core.bus, region=spiflash_region)
+
+        # Constants.
+        self.add_constant("SPIFLASH_PHY_FREQUENCY", clk_freq)
+        self.add_constant("SPIFLASH_MODULE_NAME", module.name.upper())
+        self.add_constant("SPIFLASH_MODULE_TOTAL_SIZE", module.total_size)
+        self.add_constant("SPIFLASH_MODULE_PAGE_SIZE", module.page_size)
+        if SpiNorFlashOpCodes.READ_1_1_4 in module.supported_opcodes:
+            self.add_constant("SPIFLASH_MODULE_QUAD_CAPABLE")
+        if SpiNorFlashOpCodes.READ_4_4_4 in module.supported_opcodes:
+            self.add_constant("SPIFLASH_MODULE_QPI_CAPABLE")
 
 def main():
-    soc     = MGMTSoC()
-    builder = Builder(soc, compile_software=False)
+    platforms = {
+        "caravel": CaravelPlatform
+    }
+    parser = argparse.ArgumentParser(
+        description="Caravel Management SoC"
+    )
+    parser.add_argument("--platform", default="caravel", choices=platforms.keys(),
+        help="Target platform (default=\"caravel\")" )
+    parser.add_argument("--cpu", default="vexriscv", choices=['picorv32', 'ibex', 'vexriscv'],
+        help="Main processor (default=\"vexriscv\")" )
+    parser.add_argument("--compile-software", action="store_true", help="Compile LiteX software components")
+    args = parser.parse_args()
+
+    soc     = MGMTSoC(platform_class=platforms[args.platform], cpu=args.cpu)
+    builder = Builder(soc, compile_software=args.compile_software)
     builder.build()
 
     lxsocdoc.generate_docs(soc, "build/documentation/", project_name="Caravel Management SoC", author="Efabless")
@@ -373,4 +378,4 @@ def main():
 
 
 if __name__ == "__main__":
-    main()
+    main()

litex/caravel_platform.py

@@ -158,7 +158,7 @@
 
 # Platform -----------------------------------------------------------------------------------------
 
-class Platform(GenericPlatform):
+class CaravelPlatform(GenericPlatform):
     def __init__(self, vname=""):
         GenericPlatform.__init__(self, "", _io)
 

litex/debug_reset.v

@@ -10,7 +10,6 @@
         dbg_uart_incr <= 1'd0;
         dbg_uart_address <= 32'd0;
         dbg_uart_data <= 32'd0;
-        dbg_uart_bytes_count <= 2'd0;
         dbg_uart_words_count <= 8'd0;
         dbg_uart_count <= 20'd1000000;
 	    // ******

litex/modify_verilog.py

@@ -3,9 +3,9 @@
 import os
 import sys
 
-infile = open("build/caravel_platform/gateware/mgmt_core.v","r")
+infile = open(sys.argv[1],"r")
 addfile = open("debug_reset.v","r")
-outfile = open("build/caravel_platform/gateware/mgmt_core_modified.v","wt")
+outfile = open(sys.argv[2],"wt")
 line = infile.readline()
 addline = addfile.readline()
 
@@ -48,4 +48,4 @@
 
 infile.close()
 outfile.close()
-addfile.close()
+addfile.close()

litex/requirements.txt

@@ -1,13 +1,15 @@
-git+https://github.com/enjoy-digital/litex.git
-git+https://github.com/litex-hub/litespi.git
-git+https://github.com/litex-hub/pythondata-cpu-vexriscv.git
-git+https://github.com/litex-hub/pythondata-software-picolibc.git
--e git+http://github.com/m-labs/migen.git#egg=migen
-git+https://github.com/litex-hub/pythondata-cpu-picorv32.git
-git+https://github.com/litex-hub/pythondata-cpu-ibex.git
+packaging==23.0
+-e ./third_party/litex
+-e ./third_party/litespi
+-e ./third_party/pythondata-cpu-vexriscv
+-e ./third_party/pythondata-software-picolibc
+-e ./third_party/pythondata-software-compiler_rt
+-e ./third_party/migen
+-e ./third_party/pythondata-cpu-picorv32
+-e ./third_party/pythondata-cpu-ibex
 #added to support sim_example
-git+https://github.com/enjoy-digital/litedram
-git+https://github.com/enjoy-digital/liteeth
-git+https://github.com/enjoy-digital/liteiclink
-git+https://github.com/enjoy-digital/litescope
-git+https://github.com/litex-hub/pythondata-misc-tapcfg.git
+-e ./third_party/litedram
+-e ./third_party/liteeth
+-e ./third_party/liteiclink
+-e ./third_party/litescope
+-e ./third_party/pythondata-misc-tapcfg