feature(dcd_dwc2): Added macro to cover the cache operation if they a…

…re not implemented
espressif · Nov 14, 2024 · 1799d4a · 1799d4a
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commit 1799d4a
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Showing 2 changed files with 32 additions and 21 deletions.
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -105,6 +105,16 @@ static bool _sof_en;
 //--------------------------------------------------------------------
 // DMA
 //--------------------------------------------------------------------
+// When DMA requires cache synchronization for memory
+// Data synchronization: cache to memory
+#ifndef dsync_c2m
+#define dsync_c2m(_addr, _size)
+#endif // dsync_c2m
+
+// Data synchronization: memory to cache
+#ifndef dsync_m2c
+#define dsync_m2c(_addr, _size)
+#endif // dsync_m2c
 
 TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(const dwc2_regs_t* dwc2) {
   #if !CFG_TUD_DWC2_DMA
@@ -467,9 +477,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 
     if(dma_enabled(dwc2)) {
       dep->diepdma = (uintptr_t)xfer->buffer;
-      if (total_bytes != 0) {
-        dwc2_dcd_sync_cache_to_memory(xfer->buffer, total_bytes);
-      }
+      dsync_c2m(xfer->buffer, total_bytes);
       // For ISO endpoint set correct odd/even bit for next frame.
       if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
         // Take odd/even bit from frame counter.
@@ -507,9 +515,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 
     if(dma_enabled(dwc2)) {
       dep->doepdma = (uintptr_t)xfer->buffer;
-      if (total_bytes != 0) {
-        dwc2_dcd_sync_cache_to_memory(xfer->buffer, total_bytes);
-      }
+      dsync_c2m(xfer->buffer, total_bytes);
     }
 
     dep->doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
@@ -1055,7 +1061,7 @@ static void handle_epout_irq(uint8_t rhport) {
 
         if(dma_enabled(dwc2)) {
           dma_setup_prepare(rhport);
-          dwc2_dcd_sync_memory_to_cache((uint8_t*) _setup_packet, sizeof(_setup_packet));
+          dsync_m2c((uint8_t*) _setup_packet, sizeof(_setup_packet));
         }
 
         dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
@@ -1082,9 +1088,7 @@ static void handle_epout_irq(uint8_t rhport) {
               if(epnum == 0 && xfer->total_len == 0) {
                 dma_setup_prepare(rhport);
               }
-              if (xfer->total_len) {
-                dwc2_dcd_sync_memory_to_cache(xfer->buffer, xfer->total_len);
-              }
+              dsync_m2c(xfer->buffer, xfer->total_len);
               dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
             }
           } else {

diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -109,30 +109,37 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_sync_cache_to_memory(void *add
 #if DWC2_ENABLE_MEM_CACHE
   ESP_EARLY_LOGV("dwc2_esp32", "cache to mem sync, addr 0x%"PRIx32", size %d", (uintptr_t)addr, size);
   int flags = ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED;
-  esp_err_t ret = esp_cache_msync(addr, size, flags);
-  assert(ret == ESP_OK);
+  if (addr != NULL && size) {
+    esp_err_t ret = esp_cache_msync(addr, size, flags);
+    assert(ret == ESP_OK);
+  }
 #else
-  (void)addr;
-  (void)size;
+  (void) addr;
+  (void) size;
   // nothing to do
 #endif // DWC2_ENABLE_MEM_CACHE
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_sync_memory_to_cache(void *addr, size_t size) {
 #if DWC2_ENABLE_MEM_CACHE
-  int flags = ESP_CACHE_MSYNC_FLAG_DIR_M2C;
   ESP_EARLY_LOGV("dwc2", "mem to cache sync, addr 0x%"PRIx32", size %d", (uintptr_t)addr, size);
-  // TODO: size should be multiply of CONFIG_CACHE_L1_CACHE_LINE_SIZE?
-  size = (size < CONFIG_CACHE_L1_CACHE_LINE_SIZE)? CONFIG_CACHE_L1_CACHE_LINE_SIZE : size;
-  esp_err_t ret = esp_cache_msync(addr, size, flags);
-  assert(ret == ESP_OK);
+  int flags = ESP_CACHE_MSYNC_FLAG_DIR_M2C;
+  if (addr != NULL && size) {
+    // TODO: size should be multiply of CONFIG_CACHE_L1_CACHE_LINE_SIZE?
+    size = (size < CONFIG_CACHE_L1_CACHE_LINE_SIZE)? CONFIG_CACHE_L1_CACHE_LINE_SIZE : size;
+    esp_err_t ret = esp_cache_msync(addr, size, flags);
+    assert(ret == ESP_OK);
+  }
 #else
-  (void)addr;
-  (void)size;
+  (void) addr;
+  (void) size;
   // nothing to do
 #endif // DWC2_ENABLE_MEM_CACHE
 }
 
+#define dsync_c2m(_addr, _size)   dwc2_dcd_sync_cache_to_memory((_addr), (_size))
+#define dsync_m2c(_addr, _size)   dwc2_dcd_sync_memory_to_cache((_addr), (_size))
+
 #ifdef __cplusplus
 }
 #endif