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drivers: stm32_iwdg: enable bus clock once for all
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Enable STM32 IWDG driver bus clock together with the IWDG kernel
clock when the driver is initialized. This clock is needed to propagate
IWDG early interrupt to the system.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
etienne-lms committed Dec 21, 2023
1 parent dd27de7 commit 44ed75e
Showing 1 changed file with 2 additions and 9 deletions.
11 changes: 2 additions & 9 deletions core/drivers/stm32_iwdg.c
Original file line number Diff line number Diff line change
@@ -150,34 +150,26 @@ static TEE_Result configure_timeout(struct stm32_iwdg_device *iwdg)
if (!rlr_value)
return TEE_ERROR_GENERIC;

clk_enable(iwdg->clk_pclk);

io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY);
io_write32(iwdg_base + IWDG_PR_OFFSET, IWDG_PR_DIV_256);
io_write32(iwdg_base + IWDG_RLR_OFFSET, rlr_value);
io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);

res = iwdg_wait_sync(iwdg);

clk_disable(iwdg->clk_pclk);

return res;
}

static void iwdg_start(struct stm32_iwdg_device *iwdg)
{
clk_enable(iwdg->clk_pclk);
io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_START_KEY);
clk_disable(iwdg->clk_pclk);

iwdg->flags |= IWDG_FLAGS_ENABLED;
}

static void iwdg_refresh(struct stm32_iwdg_device *iwdg)
{
clk_enable(iwdg->clk_pclk);
io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
clk_disable(iwdg->clk_pclk);
}

/* Operators for watchdog OP-TEE interface */
@@ -340,8 +332,9 @@ static TEE_Result stm32_iwdg_setup(struct stm32_iwdg_device *iwdg,
if (otp_data.disable_on_standby)
iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY;

/* Enable watchdog source clock once for all */
/* Enable watchdog source and bus clocks once for all */
clk_enable(iwdg->clk_lsi);
clk_enable(iwdg->clk_pclk);

if (otp_data.hw_enabled) {
iwdg->flags |= IWDG_FLAGS_ENABLED;

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