small test case

.github/workflows/test.yaml

@@ -23,6 +23,7 @@ jobs:
           pip install cocotb~=1.8.0
           cocotb-config --libpython
           cocotb-config --python-bin
+          pip install cocotbext-uart
 
       - name: Run tests
         run: |

test/Makefile

@@ -5,7 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+PROJECT_SOURCES = project.v fpu.v uart_rx.v uart_tx.v
 
 ifneq ($(GATES),yes)
 

test/tb.v

@@ -16,22 +16,25 @@ module tb ();
   reg clk;
   reg rst_n;
   reg ena;
+  reg rx;
   reg [7:0] ui_in;
   reg [7:0] uio_in;
   wire [7:0] uo_out;
   wire [7:0] uio_out;
   wire [7:0] uio_oe;
+  wire tx = uo_out[4];
+
 
   // Replace tt_um_example with your module name:
-  tt_um_example user_project (
+  tt_um_fstolzcode user_project (
 
       // Include power ports for the Gate Level test:
 `ifdef GL_TEST
       .VPWR(1'b1),
       .VGND(1'b0),
 `endif
 
-      .ui_in  (ui_in),    // Dedicated inputs
+      .ui_in  ({4'b0,rx,3'b0}),    // Dedicated inputs
       .uo_out (uo_out),   // Dedicated outputs
       .uio_in (uio_in),   // IOs: Input path
       .uio_out(uio_out),  // IOs: Output path

test/test.py

@@ -4,29 +4,33 @@
 import cocotb
 from cocotb.clock import Clock
 from cocotb.triggers import ClockCycles
+from cocotbext.uart import UartSource, UartSink
 
 @cocotb.test()
 async def test_adder(dut):
   dut._log.info("Start")
 
   # Our example module doesn't use clock and reset, but we show how to use them here anyway.
-  clock = Clock(dut.clk, 10, units="us")
+  clock = Clock(dut.clk, 100, units="ns")
   cocotb.start_soon(clock.start())
 
+  uart_source = UartSource(dut.rx, baud=9600, bits=8)
+  uart_sink = UartSink(dut.tx, baud=9600, bits=8)
   # Reset
   dut._log.info("Reset")
   dut.ena.value = 1
-  dut.ui_in.value = 0
-  dut.uio_in.value = 0
   dut.rst_n.value = 0
   await ClockCycles(dut.clk, 10)
   dut.rst_n.value = 1
+  await ClockCycles(dut.clk, 10)
+  await uart_source.write(b'\x81\x82\x70\x00\x82\x85\x55\x80\xA0')
+  await uart_source.wait()
+  await ClockCycles(dut.clk, 100)
+  await uart_source.write(b'\x90')
+  await uart_source.wait()
+  data = await uart_sink.read()
+  data += await uart_sink.read()
+  data += await uart_sink.read()
 
-  # Set the input values, wait one clock cycle, and check the output
-  dut._log.info("Test")
-  dut.ui_in.value = 20
-  dut.uio_in.value = 30
-
-  await ClockCycles(dut.clk, 1)
-
-  assert dut.uo_out.value == 50
+  assert data == bytearray(b'\x85c\x80')
+