fixed port and yaml

fstolzcode · Mar 12, 2024 · fbf7dab · fbf7dab
1 parent dd84a13
commit fbf7dab
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Showing 3 changed files with 7 additions and 5 deletions.
diff --git a/info.yaml b/info.yaml
@@ -27,7 +27,7 @@ pinout:
   ui[0]: ""
   ui[1]: ""
   ui[2]: ""
-  ui[3]: ""
+  ui[3]: "rx"
   ui[4]: ""
   ui[5]: ""
   ui[6]: ""
@@ -38,7 +38,7 @@ pinout:
   uo[1]: ""
   uo[2]: ""
   uo[3]: ""
-  uo[4]: ""
+  uo[4]: "tx"
   uo[5]: ""
   uo[6]: ""
   uo[7]: ""

diff --git a/src/adder.sv b/src/adder.sv
@@ -51,6 +51,7 @@ wire [15:0] be; // one front
 
 reg alu_a_c_in;
 reg alu_a_c_out;
+reg reg_alu_c_out;
 alu_a alu_a_inst(aa,ab,alu_a_c_in,ae,reg_alu_c_out);
 
 reg [15:0] bb_shift_in;
@@ -61,6 +62,7 @@ bb_shifter bb_shift_ins(bb_shift_in,bb_shift_amount,bb_left,bb_shift_out);
 
 reg alu_b_c_in;
 reg alu_b_c_out;
+reg alu_b_cout;
 alu_b alu_b_inst(ba,bb,alu_b_c_in,be,alu_b_cout);
 
 always @ (posedge clk)

diff --git a/src/alu.sv b/src/alu.sv
@@ -94,18 +94,18 @@ module alu_b (
     input [16:0] a,
     input [15:0] b,
     input c_in,
-    output [16:0] out,
+    output [15:0] out,
     output c_out
 );
     wire [16:0] b_ex = {1'b0,b[15:0]};
     wire [16:0] c;
     assign out[0] = a[0] ^ b_ex[0] ^ c_in;
     assign c[0] = (a[0] & b_ex[0]) | (a[0] & c_in) | (b_ex[0] & c_in);
     genvar i;
-    generate for(i = 1; i < 17; i = i + 1) begin
+    generate for(i = 1; i < 16; i = i + 1) begin
       assign out[i] = a[i] ^ b_ex[i] ^ c[i-1];
       assign c[i] = (a[i] & b_ex[i]) | (a[i] & c[i-1]) | (b_ex[i] & c[i-1]);
     end
-      assign c_out = c[16];
+      assign c_out = (a[16] & b_ex[16]) | (a[16] & c[15]) | (b_ex[16] & c[15]);
     endgenerate
 endmodule