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[WIP] Grate nvec paz00 #2

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[WIP] Grate nvec paz00 #2

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1436fe7
input: gpio-kbd: add driver for handling GPIO keyboard
jonasschwoebel Jan 16, 2022
b05641f
cmd: exit: add continue on key press command
clamor-s Jul 30, 2022
ac71140
cmd: ums: abort mounting by pressing any key
clamor-s Sep 16, 2022
28e435f
spi: tegra20_slink: accept any word length
clamor-s Aug 19, 2022
efcee3c
tegra30: clock: add EXTPERIPH
clamor-s Aug 19, 2022
cbe480e
tegra: lcd: video: integrate display driver for t30
ziswiler Sep 28, 2021
38532b1
video: x3: add lm3533 backlight driver
clamor-s Aug 12, 2022
1bd4fdc
video: x3: add ssd2825 bridge driver
clamor-s Aug 12, 2022
ed6b75c
video: x3: add bridge spi interface
clamor-s Aug 14, 2022
d271401
video: x3: add KOE (Hitachi) TX13D100VM0EAA panel support
clamor-s Aug 14, 2022
021ebb5
video: x3: add Renesas R69328 panel support
clamor-s Aug 14, 2022
dcc05c7
misc: extcon: add MAX14526 MUIC support
clamor-s Aug 23, 2022
9cb34ae
tegra: provide default USB gadget setup
maximschwalm Jan 23, 2022
27d0743
ARM: tegra: add late init support
clamor-s Oct 18, 2022
8a4b976
ARM: tegra: create common pre-dm i2c write
clamor-s Nov 7, 2022
71b9076
board: tegra210: use pre-dm i2c write
clamor-s Nov 7, 2022
4265132
board: tegra30: use pre-dm i2c write
clamor-s Nov 7, 2022
dbcf501
ARM: tegra: convert CONFIG_TEGRA_LP0 to Kconfig
clamor-s Mar 22, 2022
9c4eed2
ARM: tegra: expose crypto module for all Tegra SoC's
clamor-s Mar 22, 2022
53f1869
ARM: tegra: crypto: extend crypto functional
clamor-s Mar 22, 2022
01fcdce
ARM: tegra30: implement BCT patching
rmclassic Mar 22, 2022
64f93ff
ARM: tegra20: implement BCT patching
clamor-s Nov 6, 2022
48c809d
configs: tegra-common-post: add GPIO keyboard as STDIN device
clamor-s Jul 8, 2022
c34851d
disk: part_efi: add partition detection workaround for eMMC
zagto Sep 28, 2021
34a5119
fastboot: multiresponse support
IonAgorria Aug 17, 2022
921e1bf
fastboot: implement "getvar all"
IonAgorria Aug 17, 2022
9783aa1
console: separate record overflow logic and add
IonAgorria Aug 17, 2022
2b08d40
membuff: fix readline not returning line if didn't fit
IonAgorria Aug 17, 2022
04e3f2f
fastboot: add oem console and oem cmd
IonAgorria Aug 17, 2022
8300a5f
Tegra: Support Tegra20 QEMU board
digetx Oct 16, 2021
6d621e8
asus: add transformer t20 board support
clamor-s Jan 27, 2022
a870dfe
asus: transformer: add t20 based device family
clamor-s Jan 27, 2022
1ff24b5
asus: add transformer t30 board support
clamor-s Jan 27, 2022
97a25a2
asus: transformer: add t30 based device family
clamor-s Jan 27, 2022
1fbe0ab
lg: x3: Optimus 4X HD and Optimus Vu support
clamor-s Jul 10, 2022
96e6c84
ARM: tegra: remap clock_osc_freq for all Tegra family
clamor-s Oct 21, 2022
16a60bf
drivers: timer: add timer driver for ARMv7 based Tegra devices
clamor-s Oct 21, 2022
91bb6e1
ARM: tegra: include timer as default option
clamor-s Oct 21, 2022
b4f35ac
ARM: tegra: add nvec driver
marvintwentyfour Jan 25, 2020
5df65c4
ARM: tegra: add nvec keyboard driver
marvintwentyfour Jan 25, 2020
c516518
ARM: tegra: paz00: enable nvec keyboard support
marvintwentyfour Jan 25, 2020
72ae62d
i2c: tegra_nvec: Use dev_read_addr_ptr/u32_default
kwizart Apr 14, 2021
24e0735
Select CIRCBUF for TEGRA_NVEC
kwizart Nov 25, 2022
2cba2cf
Switch to DM_KEYBOARD
kwizart Nov 25, 2022
82ae625
Switch NVEC KEYBOARD to defconfig
kwizart Nov 25, 2022
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ARM: tegra: remap clock_osc_freq for all Tegra family 
Enum clock_osc_freq was designed to use only with T20.
This patch remaps it to use additional frequencies, added in
T30+ SoC while maintaining backwards compatibility with T20.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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@clamor-s
clamor-s committed Nov 25, 2022
commit 96e6c84299ec21ac3f63fb267082c9dacab5f299
9 changes: 5 additions & 4 deletions arch/arm/include/asm/arch-tegra/clock.h
View file
Original file line number Diff line number Diff line change
@@ -13,12 +13,13 @@ struct udevice;
/* Set of oscillator frequencies supported in the internal API. */
enum clock_osc_freq {
/* All in MHz, so 13_0 is 13.0MHz */
CLOCK_OSC_FREQ_13_0,
CLOCK_OSC_FREQ_19_2,
CLOCK_OSC_FREQ_12_0,
CLOCK_OSC_FREQ_26_0,
CLOCK_OSC_FREQ_13_0 = 0,
CLOCK_OSC_FREQ_16_8,
CLOCK_OSC_FREQ_19_2 = 4,
CLOCK_OSC_FREQ_38_4,
CLOCK_OSC_FREQ_12_0 = 8,
CLOCK_OSC_FREQ_48_0,
CLOCK_OSC_FREQ_26_0 = 12,

CLOCK_OSC_FREQ_COUNT,
};
17 changes: 14 additions & 3 deletions arch/arm/mach-tegra/clock.c
View file
Original file line number Diff line number Diff line change
@@ -28,16 +28,23 @@
static unsigned pll_rate[CLOCK_ID_COUNT];

/*
* The oscillator frequency is fixed to one of four set values. Based on this
* The oscillator frequency is fixed to one of seven set values. Based on this
* the other clocks are set up appropriately.
*/
static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
13000000,
16800000,
0,
0,
19200000,
12000000,
26000000,
38400000,
0,
0,
12000000,
48000000,
0,
0,
26000000,
};

/* return 1 if a peripheral ID is in range */
@@ -766,6 +773,7 @@ void tegra30_set_up_pllp(void)
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
break;
@@ -776,10 +784,13 @@ void tegra30_set_up_pllp(void)
break;

case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
break;

case CLOCK_OSC_FREQ_19_2:
case CLOCK_OSC_FREQ_38_4:
default:
/*
* These are not supported. It is too early to print a
70 changes: 56 additions & 14 deletions arch/arm/mach-tegra/cpu.c
View file
Original file line number Diff line number Diff line change
@@ -55,11 +55,18 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
*/
{
{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
* T25: 1.2 GHz
@@ -73,11 +80,18 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
*/
{
{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
* T30: 600 MHz
@@ -91,11 +105,18 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
*/
{
{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 16.8 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 38.4 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 48.0 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
* T114: 700 MHz
@@ -108,11 +129,18 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
*/
{
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 16.8 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 38.4 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 48.0 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
},

/*
@@ -126,11 +154,18 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
*/
{
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 16.8 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 38.4 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 48.0 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
},

/*
@@ -143,12 +178,19 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
* PLLX_BASE m 7: 0 8
*/
{
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz */
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 16.0 MHz = 702 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz */
{ .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz */
{ .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz */
},
};

13 changes: 5 additions & 8 deletions arch/arm/mach-tegra/tegra114/clock.c
View file
Original file line number Diff line number Diff line change
@@ -459,8 +459,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {

/*
* Get the oscillator frequency, from the corresponding hardware configuration
* field. Note that T30/T114 support 3 new higher freqs, but we map back
* to the old T20 freqs. Support for the higher oscillators is TBD.
* field. Note that T30+ supports 3 new higher freqs.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
@@ -469,12 +468,7 @@ enum clock_osc_freq clock_get_osc_freq(void)
u32 reg;

reg = readl(&clkrst->crc_osc_ctrl);
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;

if (reg & 1) /* one of the newer freqs */
printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);

return reg >> 2; /* Map to most common (T20) freqs */
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}

/* Returns a pointer to the clock source register for a peripheral */
@@ -674,6 +668,7 @@ void clock_early_init(void)
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
break;
@@ -684,10 +679,12 @@ void clock_early_init(void)
break;

case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
break;
case CLOCK_OSC_FREQ_19_2:
case CLOCK_OSC_FREQ_38_4:
default:
/*
* These are not supported. It is too early to print a
13 changes: 5 additions & 8 deletions arch/arm/mach-tegra/tegra124/clock.c
View file
Original file line number Diff line number Diff line change
@@ -601,8 +601,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {

/*
* Get the oscillator frequency, from the corresponding hardware configuration
* field. Note that Tegra30+ support 3 new higher freqs, but we map back
* to the old T20 freqs. Support for the higher oscillators is TBD.
* field. Note that T30+ supports 3 new higher freqs.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
@@ -611,12 +610,7 @@ enum clock_osc_freq clock_get_osc_freq(void)
u32 reg;

reg = readl(&clkrst->crc_osc_ctrl);
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;

if (reg & 1) /* one of the newer freqs */
printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);

return reg >> 2; /* Map to most common (T20) freqs */
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}

/* Returns a pointer to the clock source register for a peripheral */
@@ -854,6 +848,7 @@ void clock_early_init(void)
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
break;
@@ -864,10 +859,12 @@ void clock_early_init(void)
break;

case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
break;
case CLOCK_OSC_FREQ_19_2:
case CLOCK_OSC_FREQ_38_4:
default:
/*
* These are not supported. It is too early to print a
4 changes: 3 additions & 1 deletion arch/arm/mach-tegra/tegra20/clock.c
View file
Original file line number Diff line number Diff line change
@@ -399,7 +399,9 @@ enum clock_osc_freq clock_get_osc_freq(void)
u32 reg;

reg = readl(&clkrst->crc_osc_ctrl);
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;

return reg << 2;
}

/* Returns a pointer to the clock source register for a peripheral */
22 changes: 4 additions & 18 deletions arch/arm/mach-tegra/tegra210/clock.c
View file
Original file line number Diff line number Diff line change
@@ -672,8 +672,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {

/*
* Get the oscillator frequency, from the corresponding hardware configuration
* field. Note that Tegra30+ support 3 new higher freqs, but we map back
* to the old T20 freqs. Support for the higher oscillators is TBD.
* field. Note that T30+ supports 3 new higher freqs.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
@@ -682,22 +681,7 @@ enum clock_osc_freq clock_get_osc_freq(void)
u32 reg;

reg = readl(&clkrst->crc_osc_ctrl);
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
/*
* 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz,
* 8 = 12MHz, 9 = 48MHz, 12 = 26MHz
*/
if (reg == 5) {
debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg);
/* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
return 4;
}

/*
* Map to most common (T20) freqs (except 38.4, handled above):
* 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3
*/
return reg >> 2;
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}

/* Returns a pointer to the clock source register for a peripheral */
@@ -986,6 +970,7 @@ void clock_early_init(void)
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
break;
@@ -996,6 +981,7 @@ void clock_early_init(void)
break;

case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
break;
10 changes: 2 additions & 8 deletions arch/arm/mach-tegra/tegra30/clock.c
View file
Original file line number Diff line number Diff line change
@@ -439,8 +439,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {

/*
* Get the oscillator frequency, from the corresponding hardware configuration
* field. Note that T30 supports 3 new higher freqs, but we map back
* to the old T20 freqs. Support for the higher oscillators is TBD.
* field. Note that T30+ supports 3 new higher freqs.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
@@ -449,12 +448,7 @@ enum clock_osc_freq clock_get_osc_freq(void)
u32 reg;

reg = readl(&clkrst->crc_osc_ctrl);
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;

if (reg & 1) /* one of the newer freqs */
printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);

return reg >> 2; /* Map to most common (T20) freqs */
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}

/* Returns a pointer to the clock source register for a peripheral */
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