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42 Open 17 Closed
42 Open 17 Closed
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Issues list

Rewrite Yosys plugin to use Yosys's new functional backend
#100 opened Sep 24, 2024 by gussmith23
Module instance ports need HasTypes
#98 opened Aug 28, 2024 by gussmith23
@gussmith23
2RW RAM Vivado Benchmark
#97 opened Aug 19, 2024 by cknizek
2
Bitmask RAM Vivado Benchmark
#96 opened Aug 19, 2024 by cknizek
2
Tracking issue for implementing wide multiply
#94 opened Aug 3, 2024 by gussmith23
8
Do we want to delete Wire exprs in generated egglog commands?
#93 opened Jul 28, 2024 by gussmith23
Detect Wires that don't get unioned with anything in Yosys plugin
#92 opened Jul 28, 2024 by gussmith23
Important, if we're to be a real tool: need to preserve module boundaries
#91 opened Jul 22, 2024 by gussmith23
Vivado Benchmarks
#90 opened Jul 22, 2024 by cknizek
6
Flaky Verilator tests: "undefined reference to main"
#89 opened Jul 15, 2024 by gussmith23
What are Verilator's semantics when a Register sees a 1 on the clock as its first input?
#88 opened Jul 14, 2024 by gussmith23
Get DSP48E2 test working
#87 opened Jul 14, 2024 by gussmith23
Support compiling an arbitrary graph of PrimitiveInterfaces into a Lakeroad sketch
#86 opened Jul 10, 2024 by gussmith23
Call out to Lakeroad to attempt to synthesize the PrimitiveInterface
#85 opened Jul 10, 2024 by gussmith23
1
Verilator testing is still broken on Mac
#78 opened Jun 23, 2024 by gussmith23
2
Start replicating benchmarks in #76
#77 opened Jun 18, 2024 by gussmith23
List of benchmarks from Dan
#76 opened Jun 18, 2024 by gussmith23
5
Reg takes an inconsistent number of args -- does it take the clock or not?
#75 opened May 16, 2024 by gussmith23
1
Create interpreter binary
#71 opened May 9, 2024 by ninehusky
1
@ninehusky
Remove Lakeroad work from git history
#70 opened May 9, 2024 by gussmith23
Interpreter should return streams of values over time
#69 opened May 9, 2024 by gussmith23
Support get_inputs_and_outputs in the presence of cycles
#66 opened May 3, 2024 by gussmith23
Fix module instantiation compilation in Yosys Churchroad backend
#63 opened May 3, 2024 by gussmith23
If Verilog variables include keywords - it'll cause an Egglog syntax error.
#61 opened May 3, 2024 by thiskappaisgrey
Make it easier to correspond between verilog and egglog via variable names
#56 opened May 2, 2024 by gussmith23
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