Do some optimization on DSP48E2 synthesis (#303)

Makes some simplifications in the Verilog model. Also adds constraints
to the arch. description.

architecture_descriptions/xilinx_ultrascale_plus.yml

@@ -186,6 +186,24 @@ implementations:
       #"(=> (|| (bveq BREG (bv 0 32)) (bveq BREG (bv 1 32))) (bveq BCASCREG BREG))",
       # See above; same with breg.
       "(bveq BCASCREG BREG)",
+
+      # Exclude RND or P feedback loop as settings of wmux.
+      "(not (bveq (extract 8 7 OPMODE) (bv 2 2)))",
+      # "(not (bveq (extract 8 7 OPMODE) (bv 1 2)))",
+
+      # Exclude P feedback loop as setting of xmux.
+      # "(not (bveq (extract 1 0 OPMODE) (bv 2 2)))",
+
+      # I can't tell if these do more harm or good. I'm getting a bit in the
+      # weeds with solver optimization.
+      # # Exclude P feedback, PCIN, shifted PCIN/P feedback, and illegal selection (111) from Z mux.
+      # "(not (bveq (extract 6 4 OPMODE) (bv 1 3)))",
+      # # Seems like some tests may actually depend on these...
+      # # "(not (bveq (extract 6 4 OPMODE) (bv 2 3)))",
+      # # "(not (bveq (extract 6 4 OPMODE) (bv 4 3)))",
+      # "(not (bveq (extract 6 4 OPMODE) (bv 5 3)))",
+      # "(not (bveq (extract 6 4 OPMODE) (bv 6 3)))",
+      # "(not (bveq (extract 6 4 OPMODE) (bv 7 3)))",
     ]
     modules:
       - module_name: DSP48E2