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Add support for arbitrary width dsp operations #363

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@vcanumalla vcanumalla commented Sep 26, 2023

This PR adds initial support for arbitrary size DSP operations (for example, a 36 bit addition).

  • Add support for wide logical operations (AND, OR, etc.)
  • Add support for wide addition
  • Add support for wide multiplication

I don't know whether wide multiplication is going to be feasible, especially before deadline, but something to think about for the future.

This PR does not add unit tests to racket/sketches.rkt but does add integration tests.

gussmith23 added a commit that referenced this pull request Oct 24, 2023
…in `simulate_with_verilator.py` (#378)

This came up in #363.
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Looks like you need to resolve merge conflicts on this!

gussmith23 added a commit that referenced this pull request Sep 7, 2024
gussmith23 added a commit that referenced this pull request Sep 17, 2024
This is something that @vcanumalla started working on almost a year ago
as part of #363. While I may or may not get around to merging that whole
PR, at the very least, this component of that PR is very useful, so I'm
going to try to get it merged.

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Co-authored-by: Vishal Canumalla <[email protected]>
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