Fix symbol paths

iic-jku · Jan 14, 2025 · 65e5af2 · 65e5af2
1 parent ea930a1
commit 65e5af2
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/xschem/ota-5t_tb-loopgain.sch b/xschem/ota-5t_tb-loopgain.sch
@@ -198,7 +198,7 @@ C {isource.sym} 1380 -530 0 0 {name=I1 value=20u pwl(0 0 10u 0 11u 20u)"}
 C {lab_wire.sym} 1380 -300 0 1 {name=p10 sig_type=std_logic lab=v_ena}
 C {lab_pin.sym} 720 -300 0 0 {name=p11 sig_type=std_logic lab=v_ss}
 C {lab_pin.sym} 880 -300 0 0 {name=p12 sig_type=std_logic lab=v_ss}
-C {/foss/designs/analog-circuit-design/xschem/ota-5t.sym} 1340 -400 0 0 {name=x1}
+C {ota-5t.sym} 1340 -400 0 0 {name=x1}
 C {devices/vsource.sym} 1210 -280 3 0 {name=Vtest1 value="dc 0 ac 1"}
 C {lab_wire.sym} 1140 -280 0 0 {name=p3 sig_type=std_logic lab=vf1}
 C {lab_wire.sym} 1290 -280 0 0 {name=p13 sig_type=std_logic lab=vr1}
@@ -209,7 +209,7 @@ value=50f}
 C {lab_wire.sym} 1860 -430 0 0 {name=p17 sig_type=std_logic lab=v_in}
 C {isource.sym} 2140 -530 0 0 {name=I2 value=20u pwl(0 0 10u 0 11u 20u)"}
 C {lab_wire.sym} 2140 -300 0 1 {name=p18 sig_type=std_logic lab=v_ena}
-C {/foss/designs/analog-circuit-design/xschem/ota-5t.sym} 2100 -400 0 0 {name=x2}
+C {ota-5t.sym} 2100 -400 0 0 {name=x2}
 C {ammeter.sym} 2030 -280 1 0 {name=Vir1 savecurrent=true spice_ignore=0}
 C {ammeter.sym} 1930 -280 1 0 {name=Vif1 savecurrent=true spice_ignore=0}
 C {isource.sym} 1980 -210 2 0 {name=Itest1 value="dc 0 ac 1"}
@@ -220,15 +220,15 @@ value=50f}
 C {lab_wire.sym} 1100 -990 0 0 {name=p22 sig_type=std_logic lab=v_in}
 C {isource.sym} 1380 -1090 0 0 {name=I3 value=20u pwl(0 0 10u 0 11u 20u)"}
 C {lab_wire.sym} 1380 -860 0 1 {name=p23 sig_type=std_logic lab=v_ena}
-C {/foss/designs/analog-circuit-design/xschem/ota-5t.sym} 1340 -960 0 0 {name=x3}
+C {ota-5t.sym} 1340 -960 0 0 {name=x3}
 C {lab_pin.sym} 2100 -1140 0 0 {name=p26 sig_type=std_logic lab=v_dd}
 C {lab_pin.sym} 2100 -780 0 0 {name=p27 sig_type=std_logic lab=v_ss}
 C {capa.sym} 2340 -870 0 0 {name=C4
 value=50f}
 C {lab_wire.sym} 1860 -990 0 0 {name=p29 sig_type=std_logic lab=v_in}
 C {isource.sym} 2140 -1090 0 0 {name=I4 value=20u pwl(0 0 10u 0 11u 20u)"}
 C {lab_wire.sym} 2140 -860 0 1 {name=p30 sig_type=std_logic lab=v_ena}
-C {/foss/designs/analog-circuit-design/xschem/ota-5t.sym} 2100 -960 0 0 {name=x4}
+C {ota-5t.sym} 2100 -960 0 0 {name=x4}
 C {isource.sym} 1100 -750 2 1 {name=Itest3 value="dc 0 ac 0"}
 C {devices/vsource.sym} 1170 -840 3 0 {name=Vtest2 value="dc 0 ac 1"}
 C {lab_wire.sym} 1140 -800 2 0 {name=p24 sig_type=std_logic lab=vmeas1}