IR: use INV instead of XOR for bitwise invert

irmen · Jan 22, 2024 · 8f56a7f · 8f56a7f
1 parent 64c132e
commit 8f56a7f
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Showing 2 changed files with 3 additions and 17 deletions.
diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt
@@ -126,21 +126,8 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
         val code= IRCodeChunk(null, null)
         when(operator) {
             "+" -> { }
-            "-" -> {
-                code += if(address!=null)
-                    IRInstruction(Opcode.NEGM, vmDt, address = address)
-                else
-                    IRInstruction(Opcode.NEGM, vmDt, labelSymbol = symbol)
-            }
-            "~" -> {
-                val regMask = codeGen.registers.nextFree()
-                val mask = if(vmDt==IRDataType.BYTE) 0x00ff else 0xffff
-                code += IRInstruction(Opcode.LOAD, vmDt, reg1=regMask, immediate = mask)
-                code += if(address!=null)
-                    IRInstruction(Opcode.XORM, vmDt, reg1=regMask, address = address)
-                else
-                    IRInstruction(Opcode.XORM, vmDt, reg1=regMask, labelSymbol = symbol)
-            }
+            "-" -> code += IRInstruction(Opcode.NEGM, vmDt, address = address, labelSymbol = symbol)
+            "~" -> code += IRInstruction(Opcode.INVM, vmDt, address = address, labelSymbol = symbol)
             else -> throw AssemblyError("weird prefix operator")
         }
         return listOf(code)

diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
@@ -259,8 +259,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                     addInstr(result, IRInstruction(Opcode.NEG, vmDt, reg1 = tr.resultReg), null)
             }
             "~" -> {
-                val mask = if(vmDt==IRDataType.BYTE) 0x00ff else 0xffff
-                addInstr(result, IRInstruction(Opcode.XOR, vmDt, reg1 = tr.resultReg, immediate = mask), null)
+                addInstr(result, IRInstruction(Opcode.INV, vmDt, reg1 = tr.resultReg), null)
             }
             else -> throw AssemblyError("weird prefix operator")
         }