get rid of certain redundant !=0 comparisons in logical expressions

irmen · Feb 1, 2024 · c71aa08 · c71aa08
1 parent 9f8e617
commit c71aa08
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Showing 2 changed files with 21 additions and 4 deletions.
diff --git a/compiler/src/prog8/compiler/astprocessing/VariousCleanups.kt b/compiler/src/prog8/compiler/astprocessing/VariousCleanups.kt
@@ -151,6 +151,27 @@ internal class VariousCleanups(val program: Program, val errors: IErrorReporter,
                 }
             }
         }
+
+        if(expr.operator in LogicalOperators) {
+            // remove redundant !=0 comparisons from logical expressions such as:   a!=0 xor b --> a xor b  (only for byte operands!)
+            val leftExpr = expr.left as? BinaryExpression
+            if(leftExpr != null &&
+                leftExpr.operator == "!=" &&
+                !leftExpr.left.isSimple &&
+                leftExpr.left.inferType(program).isBytes &&
+                leftExpr.right.constValue(program)?.number == 0.0) {
+                return listOf(IAstModification.ReplaceNode(leftExpr, leftExpr.left, expr))
+            }
+            val rightExpr = expr.right as? BinaryExpression
+            if(rightExpr != null &&
+                rightExpr.operator == "!=" &&
+                !rightExpr.left.isSimple &&
+                rightExpr.left.inferType(program).isBytes &&
+                rightExpr.right.constValue(program)?.number == 0.0) {
+                return listOf(IAstModification.ReplaceNode(rightExpr, rightExpr.left, expr))
+            }
+        }
+
         return noModifications
     }
 

diff --git a/docs/source/todo.rst b/docs/source/todo.rst
@@ -1,10 +1,6 @@
 TODO
 ====
 
-maze:   if cell & UP!=0 and @(celladdr(cx,cy-1)) & (WALKED|BACKTRACKED) ==0
-              ^^ adding this !=0 caused a weird beq + / lda #1 / +  to appear in front of the shortcircuit beq...
-
-
 (after merge in boolean): move all "OperatorXinplace" from expressionGen to AssignmentGen, see if we can get rid of the Result return type.
 
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