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FPGA+SIM: updated Vivado project to compile RISC-V simulation, access… #198

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FPGA+SIM: updated Vivado project to compile RISC-V simulation, access…

FPGA+SIM: updated Vivado project to compile RISC-V simulation, access… #198

Triggered via push August 19, 2023 15:25
@jerasjeras
pushed c92b5ac
master
Status Success
Total duration 1m 17s
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The following actions uses node12 which is deprecated and will be forced to run on node16: actions/checkout@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/

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