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This source code concerns the development of a Harvard 16 bits microcontroller based in the MIPS microprocessors. The microcontroller was developed entirely in VHDL and implemented in a Cyclone II FPGA donated by Altera. It has a reduced instruction set of constant size. This last characteristic facilitated the inclusion of a pipeline with five …

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.hg
.hg
 
 
LCD
LCD
 
 
Timer
Timer
 
 
app
app
 
 
assembler
assembler
 
 
eia232
eia232
 
 
mac
mac
 
 
programador
programador
 
 
2011_REIC.pdf
2011_REIC.pdf
 
 
2011_SFORUM.pdf
2011_SFORUM.pdf
 
 
BancoInterrup.vhd
BancoInterrup.vhd
 
 
LICENSE
LICENSE
 
 
README.md
README.md
 
 
RegEXMEM.vhd
RegEXMEM.vhd
 
 
RegIDEX.vhd
RegIDEX.vhd
 
 
RegIFID.vhd
RegIFID.vhd
 
 
RegMEMWB.vhd
RegMEMWB.vhd
 
 
anem16.vhd
anem16.vhd
 
 
controladorCache.vhd
controladorCache.vhd
 
 
controladorRAM.vhd
controladorRAM.vhd
 
 
controladorSharedSRAM.vhd
controladorSharedSRAM.vhd
 
 
controle.vhd
controle.vhd
 
 
decoder.vhd
decoder.vhd
 
 
forwarding_unit.vhd
forwarding_unit.vhd
 
 
hazard_unit.vhd
hazard_unit.vhd
 
 
int_reg.vhd
int_reg.vhd
 
 
interrupcoes.vhd
interrupcoes.vhd
 
 
lookahead_unit.vhd
lookahead_unit.vhd
 
 
microcontrolador.vhd
microcontrolador.vhd
 
 
mips_adder.vhd
mips_adder.vhd
 
 
mips_alu.vhd
mips_alu.vhd
 
 
mux.vhd
mux.vhd
 
 
nbit_adder.vhd
nbit_adder.vhd
 
 
perifericos.vhd
perifericos.vhd
 
 
ram.vhd
ram.vhd
 
 
regDATA.vhd
regDATA.vhd
 
 
regINT.vhd
regINT.vhd
 
 
reg_file.vhd
reg_file.vhd
 
 
rf_registrador.vhd
rf_registrador.vhd
 
 
rom_ip.vhd
rom_ip.vhd
 
 
sete.vhd
sete.vhd
 
 
simulRAM.vhd
simulRAM.vhd
 
 
std_logic_textio.vhd
std_logic_textio.vhd
 
 
teste_interrup.vhd
teste_interrup.vhd
 
 
uregistrador.vhd
uregistrador.vhd
 
 

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ANEM-TG

This source code concerns the development of a Harvard 16 bits microcontroller based in the MIPS microprocessors. The microcontroller was developed entirely in VHDL and implemented in a Cyclone II FPGA donated by Altera. It has a reduced instruction set of constant size. This last characteristic facilitated the inclusion of a pipeline with five stages. Peripherals are disposed in a modular way that permits easy addition or deletion of new elements using a simple mapping of data memory.

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This source code concerns the development of a Harvard 16 bits microcontroller based in the MIPS microprocessors. The microcontroller was developed entirely in VHDL and implemented in a Cyclone II FPGA donated by Altera. It has a reduced instruction set of constant size. This last characteristic facilitated the inclusion of a pipeline with five …

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