GitHub - jsheo96/lab6: Architecture lab6

Name		Name	Last commit message	Last commit date
Latest commit History 14 Commits
.gitignore		.gitignore
ADD.v		ADD.v
ALU.v		ALU.v
ALUControl.v		ALUControl.v
BTB.v		BTB.v
ControlUnit.v		ControlUnit.v
DiscardInstruction.v		DiscardInstruction.v
EXMEM_Register.v		EXMEM_Register.v
Flush.v		Flush.v
ForwardingUnit.v		ForwardingUnit.v
IDEX_Register.v		IDEX_Register.v
IFID_Register.v		IFID_Register.v
JLControlBlock.v		JLControlBlock.v
JRControlBlock.v		JRControlBlock.v
LRU_Register.v		LRU_Register.v
MEMWB_Register.v		MEMWB_Register.v
Memory.v		Memory.v
Memory_normal.v		Memory_normal.v
Multiplexer16bit2to1.v		Multiplexer16bit2to1.v
Multiplexer16bit4to1.v		Multiplexer16bit4to1.v
Multiplexer17bit2to1.v		Multiplexer17bit2to1.v
Multiplexer2bit2to1.v		Multiplexer2bit2to1.v
Multiplexer2bit4to1.v		Multiplexer2bit4to1.v
PC_Register.v		PC_Register.v
Predictor.v		Predictor.v
README.md		README.md
RegisterFile.v		RegisterFile.v
SignExtend.v		SignExtend.v
StallUnit.v		StallUnit.v
cache.v		cache.v
cpu.v		cpu.v
cpu_TB.v		cpu_TB.v
cpu_TB_normal.v		cpu_TB_normal.v
eviction_selector.v		eviction_selector.v
wlftk6z40t		wlftk6z40t
wlftnh4grb		wlftnh4grb
wlftwz0hw4		wlftwz0hw4

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"# Architecture-lab5"