Week 2 Lab: System Verilog

Exercise 3: Make Note: The different testing approaches IMO are the result of the fact that some module only need edge case testing, some modules need thourogh testing, and some need only random testing. To elaborate: in some cases we only care about certain behaviors, like the cycling of states. In other cases the output is based on input only, so it's easier and better to toroughly test. Sometimes random testing is enough to validate correct behavior, eg. 0 = false, not-0 = true.