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  1. openlane-examples openlane-examples Public

    Examples from the Openlane repository, adapted as Fusesoc cores

    Verilog 11 4

  2. chip_integration_test chip_integration_test Public

    Verilog 4 1

  3. subservient_wrapped subservient_wrapped Public

    The Subservient processor wrapped together with some memory for inclusion in the Caravel user project area.

    Verilog 2 1

  4. caravel_subservient caravel_subservient Public

    Forked from efabless/caravel_user_project

    https://caravel-user-project.readthedocs.io

    Verilog 2

  5. caravel_user_project caravel_user_project Public

    Verilog 2

  6. blinky blinky Public

    Forked from fusesoc/blinky

    Example LED blinking project for your FPGA dev board of choice

    Verilog 1

12 contributions in the last year

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Activity overview

Loading A graph representing klasnordmark's contributions from February 25, 2024 to February 25, 2025. The contributions are 100% commits, 0% issues, 0% pull requests, 0% code review.

Contribution activity

February 2025

1 contribution in private repositories Feb 19
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