A Reduced Instruction Set Computer (RISC) is a microprocessor architecture that utilizes a small number of simple and generalized instructions rather than complex and specialized ones.
This microprocessor has been developed in the Verilog hardware description language, simulated on the Xilinx ISE and tested on the Spartan 3 FPGA.
This is a top level overview of the microprocessor.
This RISC processor uses 32-bit instructions. The division of the 32-bit instructions has been inspired by the MIPS architecture.
The instruction set architecture of the processor to mirror the functions of the MIPS microprocessor architecture.
This processor is a joint project by
Refer to documentation for implementation details.