Made export port be output by default when direction undefined.

lip6 · Dec 7, 2023 · ee22519 · ee22519
1 parent 28020c4
commit ee22519
Showing 1 changed file with 1 addition and 6 deletions.
diff --git a/crlcore/src/ccore/verilog/VerilogDriver.cpp b/crlcore/src/ccore/verilog/VerilogDriver.cpp
@@ -243,15 +243,10 @@ namespace CRL {
       {
         out << "  inout ";
       }
-      else if (dir == Net::Direction::OUT)
+      else // if direction undefined assume it is output
       {
         out << "  output ";
       }
-      else
-      {
-        std::cerr << "Undetermined direction " << dir << " for the net \"" << name << "\"" << std::endl;
-        assert(false);
-      }
       if (idx_min >= 0)
       {
         out << "[" << idx_max << ":" << idx_min << "] ";