[AMDGPU] Add Wave Reduce Intrinsics for i32 type #111342
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| @@ -2119,8 +2119,14 @@ class AMDGPUWaveReduce<LLVMType data_ty = llvm_anyint_ty> : Intrinsic< | |||
| ], | |||
| [IntrNoMem, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree, ImmArg<ArgIndex<1>>]>; | |||
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| def int_amdgcn_wave_reduce_umin : AMDGPUWaveReduce; | |||
| def int_amdgcn_wave_reduce_umax : AMDGPUWaveReduce; | |||
| multiclass AMDGPUWaveReduceGenerator<list<string> Operations> { | |||
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Rename Operations with WaveReduceOps ?
| case AMDGPU::S_SUB_I32: | ||
| case AMDGPU::S_OR_B32: | ||
| case AMDGPU::S_XOR_B32: | ||
| return 0x00000000; |
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Literal values are not consistent form here (0, 0x00000000, 0xFFFFFFFF). Can we not query this using std::numeric_limits here also?
| const TargetRegisterClass *WaveMaskRegClass = TRI->getWaveMaskRegClass(); | ||
| const TargetRegisterClass *DstRegClass = MRI.getRegClass(DstReg); | ||
| Register ExecMask = MRI.createVirtualRegister(WaveMaskRegClass); | ||
| Register CountOfActiveLanesReg = MRI.createVirtualRegister(DstRegClass); |
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Just ActiveLanes ? In general, you are mangling type in your variable names everywhere. we can avoid that.
Currently, wave wide reduction is supported for
uminandumaxoperations only.This patch extends the support for:
uadd,add,usub,sub,min,max,and,or,xorops fori32type.