Merge pull request #359 from lnis-uofu/pin_constraint_polarity

Add Test Cases for the Signal Polarity Support in Pin Constraint Files
lnis-uofu · Jul 3, 2021 · 223e06d · 223e06d
2 parents b8bed59 + 9f03ecb
commit 223e06d
Show file tree

Hide file tree

Showing 32 changed files with 348 additions and 189 deletions.
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -105,6 +105,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
                                                            const std::string& reference_verilog_top_name,
                                                            const AtomContext& atom_ctx,
                                                            const VprNetlistAnnotation& netlist_annotation,
+                                                           const PinConstraints& pin_constraints,
                                                            const bool& explicit_port_mapping) {
   /* Validate the file stream */
   valid_file_stream(fp);
@@ -125,6 +126,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
                                              prefix_to_remove,
                                              std::string(BENCHMARK_PORT_POSTFIX),
                                              atom_ctx, netlist_annotation,
+                                             pin_constraints,
                                              explicit_port_mapping);
 
   print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@@ -155,6 +157,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
                                              std::vector<std::string>(),
                                              std::string(FPGA_PORT_POSTFIX),
                                              atom_ctx, netlist_annotation,
+                                             PinConstraints(),
                                              explicit_port_mapping);
 
   print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
@@ -213,10 +216,6 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp,
     if (1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager,  pin_constraints.net_pin(block_name)))) {
       initial_value = 0;
     }
-    /* Pin constraints has the final decision on the default value */
-    if (pin_constraints.valid_net_default_value(block_name)) {
-      initial_value = pin_constraints.net_default_value_to_int(block_name);
-    }
 
     fp << "initial" << std::endl;
     fp << "\tbegin" << std::endl;
@@ -308,6 +307,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
   if (!options.no_self_checking()) {
     print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name,
                                                           atom_ctx, netlist_annotation,
+                                                          pin_constraints,
                                                           options.explicit_port_mapping());
   }
 

diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -69,6 +69,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
                                                 const std::string& output_port_postfix,
                                                 const AtomContext& atom_ctx,
                                                 const VprNetlistAnnotation& netlist_annotation,
+                                                const PinConstraints& pin_constraints,
                                                 const bool& use_explicit_port_map) {
   /* Validate the file stream */
   valid_file_stream(fp);
@@ -99,6 +100,15 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
       if (true == use_explicit_port_map) {
         fp << "." << block_name << module_input_port_postfix << "(";
       }
+
+      /* Polarity of some input may have to be inverted, as defined in pin constraints
+       * For example, the reset signal of the benchmark is active low 
+       * while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted)
+       * However, to ensure correct stimuli to the benchmark, we have to invert the signal
+       */
+      if (PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(block_name)) {
+        fp << "~";
+      }
       fp << block_name;
       if (true == use_explicit_port_map) {
         fp << ")";

diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
@@ -38,6 +38,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
                                                 const std::string& output_port_postfix,
                                                 const AtomContext& atom_ctx,
                                                 const VprNetlistAnnotation& netlist_annotation,
+                                                const PinConstraints& pin_constraints,
                                                 const bool& use_explicit_port_map);
 
 void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,

diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -912,6 +912,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
                                                     const std::string& reference_verilog_top_name,
                                                     const AtomContext& atom_ctx,
                                                     const VprNetlistAnnotation& netlist_annotation,
+                                                    const PinConstraints& pin_constraints,
                                                     const bool& explicit_port_mapping) {
   /* Validate the file stream */
   valid_file_stream(fp);
@@ -932,6 +933,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
                                              prefix_to_remove,
                                              std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
                                              atom_ctx, netlist_annotation,
+                                             pin_constraints,
                                              explicit_port_mapping);
 
   print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@@ -1789,11 +1791,7 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp,
       continue;
     }
 
-    /* Pin constraints has the final decision on the default value */
     size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)));
-    if (pin_constraints.valid_net_default_value(block_name)) {
-      initial_value = pin_constraints.net_default_value_to_int(block_name);
-    }
 
     /* Connect stimuli to greset with an optional inversion, depending on the default value */
     BasicPort reset_port(block_name, 1);
@@ -2004,6 +2002,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
                                                    circuit_name,
                                                    atom_ctx,
                                                    netlist_annotation,
+                                                   pin_constraints,
                                                    explicit_port_mapping);
   }
 

diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act b/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act
diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif b/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif
diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v b/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v
diff --git a/...mark/counter_128bit_async_reset/counter.v → ...ters/counter_128bit_async_reset/counter.v b/...mark/counter_128bit_async_reset/counter.v → ...ters/counter_128bit_async_reset/counter.v
diff --git a/...k/counter_128bit_async_reset/counter_tb.v → ...s/counter_128bit_async_reset/counter_tb.v b/...k/counter_128bit_async_reset/counter_tb.v → ...s/counter_128bit_async_reset/counter_tb.v
diff --git a/...ark/counter_128bit_async_resetb/counter.v → ...ers/counter_128bit_async_resetb/counter.v b/...ark/counter_128bit_async_resetb/counter.v → ...ers/counter_128bit_async_resetb/counter.v
diff --git a/.../counter_128bit_async_resetb/counter_tb.v → .../counter_128bit_async_resetb/counter_tb.v b/.../counter_128bit_async_resetb/counter_tb.v → .../counter_128bit_async_resetb/counter_tb.v
diff --git a/...k/counter4bit_2clock/counter4bit_2clock.v → ...counter_4bit_2clock/counter_4bit_2clock.v b/...k/counter4bit_2clock/counter4bit_2clock.v → ...counter_4bit_2clock/counter_4bit_2clock.v
@@ -1,4 +1,4 @@
-module counter4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
+module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
 
     input clk0;
     input rst0;

diff --git a/...ounter4bit_2clock/counter4bit_2clock_tb.v → ...nter_4bit_2clock/counter_4bit_2clock_tb.v b/...ounter4bit_2clock/counter4bit_2clock_tb.v → ...nter_4bit_2clock/counter_4bit_2clock_tb.v
@@ -1,17 +1,17 @@
-module counter4bit_2clock_tb;
+module counter_4bit_2clock_tb;
 
 	reg clk0, rst0;
 	wire [3:0] q0;
 
 	reg clk1, rst1;
 	wire [3:0] q1;
 
-	counter_2clock C_1(
+	counter_4bit_2clock C_1(
 		clk0, 
 		q0, 
 		rst0);
 
-	counter_2clock C_1(
+	counter_4bit_2clock C_1(
 		clk1, 
 		q1, 
 		rst1);

diff --git a/...o_benchmark/counter_async_reset/counter.v → ...unters/counter_8bit_async_reset/counter.v b/...o_benchmark/counter_async_reset/counter.v → ...unters/counter_8bit_async_reset/counter.v
diff --git a/...enchmark/counter_async_reset/counter_tb.v → ...ers/counter_8bit_async_reset/counter_tb.v b/...enchmark/counter_async_reset/counter_tb.v → ...ers/counter_8bit_async_reset/counter_tb.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
@@ -0,0 +1,25 @@
+///////////////////////////////////////////
+//  Functionality: Counter with asynchronous reset
+//  Author:        Xifan Tang
+////////////////////////////////////////
+
+module counter (
+	clk,
+	resetb,
+	result
+);
+
+	input clk;
+	input resetb;
+	output [7:0] result;
+
+	reg [7:0] result;
+
+	always @(posedge clk or negedge resetb)
+	begin
+		if (!resetb) 
+			result = 0;		
+		else 
+			result = result + 1;
+	end
+endmodule		
diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v
@@ -0,0 +1,25 @@
+module counter_tb;
+
+  reg clk, resetb;
+  wire [7:0] result;
+
+  counter DUT(
+    .clk(clk), 
+    .resetb(resetb), 
+    .result(result)
+  );
+
+  initial begin
+    #0 resetb = 1'b0; clk = 1'b0;
+    #100 resetb = 1'b1;
+  end
+
+  always begin
+    #10 clk = ~clk;
+  end
+
+  initial begin
+    #5000 $stop;
+  end
+
+endmodule
diff --git a/...chmarks/micro_benchmark/counter/counter.v → ...ounters/counter_8bit_sync_reset/counter.v b/...chmarks/micro_benchmark/counter/counter.v → ...ounters/counter_8bit_sync_reset/counter.v
diff --git a/...arks/micro_benchmark/counter/counter_tb.v → ...ters/counter_8bit_sync_reset/counter_tb.v b/...arks/micro_benchmark/counter/counter_tb.v → ...ters/counter_8bit_sync_reset/counter_tb.v
diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
@@ -139,15 +139,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
+    <circuit_model type="ff" name="MULTI_MODE_DFFRQ" prefix="MULTI_MODE_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/>
        <port type="output" prefix="Q" size="1"/>
        <port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/>
+       <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
     </circuit_model>
     <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
       <design_technology type="cmos" fracturable_lut="true"/>
@@ -220,20 +220,34 @@
     </pb_type>
     <pb_type name="clb.fle" physical_mode_name="physical"/>
     <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFRQ" mode_bits="0"/>
     <!-- Binding operating pb_type to physical pb_type -->
     <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
       <port name="in" physical_mode_port="in[0:2]"/>
       <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
     </pb_type>
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0">
+      <port name="clk" physical_mode_port="C"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1">
+      <port name="RN" physical_mode_port="R"/>
+    </pb_type>
     <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
       <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
       <port name="in" physical_mode_port="in[0:3]"/>
       <port name="out" physical_mode_port="lut4_out"/>
     </pb_type>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
+      <port name="clk" physical_mode_port="C"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
+      <port name="RN" physical_mode_port="R"/>
+    </pb_type>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>