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Merge pull request #359 from lnis-uofu/pin_constraint_polarity
Add Test Cases for the Signal Polarity Support in Pin Constraint Files
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openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act
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openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif
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openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v
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...k/counter4bit_2clock/counter4bit_2clock.v → ...counter_4bit_2clock/counter_4bit_2clock.v
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...ounter4bit_2clock/counter4bit_2clock_tb.v → ...nter_4bit_2clock/counter_4bit_2clock_tb.v
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openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
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Original file line number | Diff line number | Diff line change |
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/////////////////////////////////////////// | ||
// Functionality: Counter with asynchronous reset | ||
// Author: Xifan Tang | ||
//////////////////////////////////////// | ||
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module counter ( | ||
clk, | ||
resetb, | ||
result | ||
); | ||
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input clk; | ||
input resetb; | ||
output [7:0] result; | ||
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reg [7:0] result; | ||
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always @(posedge clk or negedge resetb) | ||
begin | ||
if (!resetb) | ||
result = 0; | ||
else | ||
result = result + 1; | ||
end | ||
endmodule |
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openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v
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module counter_tb; | ||
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reg clk, resetb; | ||
wire [7:0] result; | ||
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counter DUT( | ||
.clk(clk), | ||
.resetb(resetb), | ||
.result(result) | ||
); | ||
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initial begin | ||
#0 resetb = 1'b0; clk = 1'b0; | ||
#100 resetb = 1'b1; | ||
end | ||
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always begin | ||
#10 clk = ~clk; | ||
end | ||
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initial begin | ||
#5000 $stop; | ||
end | ||
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endmodule |
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