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Release of OpenFPGA framework

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@tangxifan tangxifan released this 27 Nov 23:26
· 7440 commits to master since this release
v0.3-alpha
49a8273
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This release is for the following papers:

  • X. Tang, E. Giacomin, A. Alacchi, B. Chauviere and P.-E. Gaillardon, "OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs," 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, 2019, pp. 367-374.
  • X. Tang, E. Giacomin, A. Alacchi and P.-E. Gaillardon, "A Study on Switch Block Patterns for
    Tileable FPGA Routing Architectures", International Conference on Field-Programmable Technology (FPT), Tianjin, China, 2019, pp. 1-4.

What is new:

  • Full support on Verilog generation and bitstream generation for multi-mode CLB architectures
  • Experimental support for multi-mode heterogeneous blocks
  • Experimental support for tileable routing architecture generation
  • Upgraded Verilog testbenches which include auto-check flags to ease the verification
  • Validated over MCNC big20, EPFL benchmarks, and picoRV32 (https://github.com/cliffordwolf/picorv32)
  • Tested over opensource iVerilog simulator and Mentor ModelSim
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