[top] Regenerate tops with ipgen'ed rv_core_ibex

Signed-off-by: Robert Schilling <[email protected]>

hw/top_darjeeling/data/autogen/defs.bzl

@@ -29,7 +29,7 @@ load("//hw/top_darjeeling/ip_autogen/pinmux:defs.bzl", "PINMUX")
 load("//hw/top_darjeeling/ip_autogen/pwrmgr:defs.bzl", "PWRMGR")
 load("//hw/ip/rom_ctrl:defs.bzl", "ROM_CTRL")
 load("//hw/top_darjeeling/ip_autogen/rstmgr:defs.bzl", "RSTMGR")
-load("//hw/ip/rv_core_ibex:defs.bzl", "RV_CORE_IBEX")
+load("//hw/top_darjeeling/ip_autogen/rv_core_ibex:defs.bzl", "RV_CORE_IBEX")
 load("//hw/ip/rv_dm:defs.bzl", "RV_DM")
 load("//hw/top_darjeeling/ip_autogen/rv_plic:defs.bzl", "RV_PLIC")
 load("//hw/ip/rv_timer:defs.bzl", "RV_TIMER")

hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson

@@ -9320,6 +9320,12 @@
     {
       name: rv_core_ibex
       type: rv_core_ibex
+      template_type: rv_core_ibex
+      attr: ipgen
+      ipgen_param:
+      {
+        NumRegions: 32
+      }
       param_decl:
       {
         PMPEnable: "1"
@@ -11482,7 +11488,7 @@
               {
                 hart: 0x211f0000
               }
-              size_byte: 0x100
+              size_byte: 0x800
             }
           ]
           xbar: false

hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv

@@ -59,7 +59,7 @@ tl_device_t xbar_devices[$] = '{
         '{32'h21140000, 32'h211400ff}
     }},
     '{"rv_core_ibex__cfg", '{
-        '{32'h211f0000, 32'h211f00ff}
+        '{32'h211f0000, 32'h211f07ff}
     }},
     '{"sram_ctrl_main__regs", '{
         '{32'h211c0000, 32'h211c003f}

hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg

@@ -88,7 +88,7 @@
 -node tb.dut*.u_keymgr_dpe tl_*i.a_address[23:21]
 -node tb.dut*.u_keymgr_dpe tl_*i.a_address[28:25]
 -node tb.dut*.u_keymgr_dpe tl_*i.a_address[31:30]
--node tb.dut*.u_rv_core_ibex cfg_tl_*i.a_address[15:8]
+-node tb.dut*.u_rv_core_ibex cfg_tl_*i.a_address[15:11]
 -node tb.dut*.u_rv_core_ibex cfg_tl_*i.a_address[23:21]
 -node tb.dut*.u_rv_core_ibex cfg_tl_*i.a_address[28:25]
 -node tb.dut*.u_rv_core_ibex cfg_tl_*i.a_address[31:30]

hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson

@@ -632,7 +632,7 @@
           {
             hart: 0x211f0000
           }
-          size_byte: 0x100
+          size_byte: 0x800
         }
       ]
       xbar: false

hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg

@@ -86,7 +86,7 @@
 -node tb.dut tl_keymgr_dpe_o.a_address[23:21]
 -node tb.dut tl_keymgr_dpe_o.a_address[28:25]
 -node tb.dut tl_keymgr_dpe_o.a_address[31:30]
--node tb.dut tl_rv_core_ibex__cfg_o.a_address[15:8]
+-node tb.dut tl_rv_core_ibex__cfg_o.a_address[15:11]
 -node tb.dut tl_rv_core_ibex__cfg_o.a_address[23:21]
 -node tb.dut tl_rv_core_ibex__cfg_o.a_address[28:25]
 -node tb.dut tl_rv_core_ibex__cfg_o.a_address[31:30]

hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv

@@ -62,7 +62,7 @@ tl_device_t xbar_devices[$] = '{
         '{32'h21140000, 32'h211400ff}
     }},
     '{"rv_core_ibex__cfg", '{
-        '{32'h211f0000, 32'h211f00ff}
+        '{32'h211f0000, 32'h211f07ff}
     }},
     '{"sram_ctrl_main__regs", '{
         '{32'h211c0000, 32'h211c003f}

hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv

@@ -63,7 +63,7 @@ package tl_main_pkg;
   localparam logic [31:0] ADDR_MASK_RV_PLIC              = 32'h 07ffffff;
   localparam logic [31:0] ADDR_MASK_OTBN                 = 32'h 0000ffff;
   localparam logic [31:0] ADDR_MASK_KEYMGR_DPE           = 32'h 000000ff;
-  localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX__CFG    = 32'h 000000ff;
+  localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX__CFG    = 32'h 000007ff;
   localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__REGS = 32'h 0000003f;
   localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__RAM  = 32'h 0000ffff;
   localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MBOX__REGS = 32'h 0000003f;

hw/top_darjeeling/ip_autogen/rv_core_ibex/BUILD

@@ -0,0 +1,19 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+    name = "rtl_files",
+    srcs = glob(
+        ["**"],
+        exclude = [
+            "dv/**",
+            "doc/**",
+            "README.md",
+        ],
+    ) + [
+        "//hw/darjeeling/ip_autogen/rv_core_ibex/data:all_files",
+    ],
+)

hw/top_darjeeling/ip_autogen/rv_core_ibex/README.md

@@ -0,0 +1,32 @@
+# Ibex RISC-V Core Wrapper Technical Specification
+
+[`rv_core_ibex`](https://ibex.reports.lowrisc.org/opentitan/latest/report.html):
+![](https://dashboards.lowrisc.org/badges/dv/ibex/opentitan/test.svg)
+![](https://dashboards.lowrisc.org/badges/dv/ibex/opentitan/passing.svg)
+![](https://dashboards.lowrisc.org/badges/dv/ibex/opentitan/functional.svg)
+![](https://dashboards.lowrisc.org/badges/dv/ibex/opentitan/code.svg)
+
+# Overview
+
+This document specifies Ibex CPU core wrapper functionality.
+
+## Features
+
+* Instantiation of a [Ibex RV32 CPU Core](https://github.com/lowRISC/ibex).
+* TileLink Uncached Light (TL-UL) host interfaces for the instruction and data ports.
+* Simple address translation.
+* NMI support for security alert events for watchdog bark.
+* General error status collection and alert generation.
+* Crash dump collection for software debug.
+
+## Description
+
+The Ibex RISC-V Core Wrapper instantiates an [Ibex RV32 CPU Core](https://github.com/lowRISC/ibex), and wraps its data and instruction memory interfaces to TileLink Uncached Light (TL-UL).
+All configuration parameters of Ibex are passed through.
+The pipelining of the bus adapters is configurable.
+
+## Compatibility
+
+Ibex is a compliant RV32 RISC-V CPU core, as [documented in the Ibex documentation](https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html).
+
+The TL-UL bus interfaces exposed by this wrapper block are compliant to the [TileLink Uncached Lite Specification version 1.7.1](https://sifive.cdn.prismic.io/sifive%2F57f93ecf-2c42-46f7-9818-bcdd7d39400a_tilelink-spec-1.7.1.pdf).