[doc] Fix links to rv_core_ibex

Signed-off-by: Robert Schilling <[email protected]>

BLOCKFILE

@@ -56,7 +56,6 @@ hw/ip/prim_xilinx/rtl/*
 hw/ip/prim_xilinx_ultrascale/rtl/*
 hw/ip/pwm/rtl/*
 hw/ip/rom_ctrl/rtl/*
-hw/ip/rv_core_ibex/rtl/*
 hw/ip/rv_dm/rtl/*
 hw/ip/rv_timer/rtl/*
 hw/ip/spi_device/rtl/*
@@ -104,7 +103,6 @@ hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson
 hw/top_earlgrey/data/otp/otp_ctrl_img_test_unlocked1.hjson
 hw/top_earlgrey/data/otp/otp_ctrl_img_prod.hjson
 hw/top_earlgrey/data/otp/otp_ctrl_img_test_unlocked2.hjson
-hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
 hw/ip/pwm/data/pwm.hjson
 hw/ip/aon_timer/data/aon_timer.hjson
 
@@ -116,6 +114,7 @@ hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson
 hw/top_earlgrey/ip_autogen/pwrmgr/data/pwrmgr.hjson
 hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson
 hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson
+hw/top_earlgrey/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson
 
 hw/top_earlgrey/data/top_earlgrey.hjson
 hw/top_earlgrey/data/xbar_main.hjson

SUMMARY.md

@@ -64,6 +64,13 @@
     - [Registers](./hw/top_earlgrey/ip/sensor_ctrl/doc/registers.md)
     - [Device Interface Functions](./sw/device/lib/dif/dif_sensor_ctrl.h)
     - [Checklist](./hw/top_earlgrey/ip/sensor_ctrl/doc/checklist.md)
+  - [Ibex RISC-V Core Wrapper](./hw/top_earlgrey/ip_autogen/rv_core_ibex/README.md)
+    - [Theory of Operation](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/theory_of_operation.md)
+    - [Design Verification](./hw/top_earlgrey/ip_autogen/rv_core_ibex/dv/README.md)
+    - [Programmer's Guide](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/programmers_guide.md)
+    - [Hardware Interfaces](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/interfaces.md)
+    - [Registers](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/registers.md)
+    - [Checklist](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/checklist.md)
   - [TL-UL Checklist](./hw/top_earlgrey/ip/xbar/doc/checklist.md)
   - [Pinmux Targets](./hw/top_earlgrey/ip_autogen/pinmux/doc/targets.md)
     - [ASIC Target Pinout and Pinmux Connectivity](./hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md)
@@ -81,15 +88,22 @@
     - [Registers](./hw/top_darjeeling/ip_autogen/otp_ctrl/doc/registers.md)
     - [Device Interface Functions](./sw/device/lib/dif/dif_otp_ctrl.h)
     - [Checklist](./hw/top_darjeeling/ip_autogen/otp_ctrl/doc/checklist.md)
+  - [Ibex RISC-V Core Wrapper](./hw/top_darjeeling/ip_autogen/rv_core_ibex/README.md)
+    - [Theory of Operation](./hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/theory_of_operation.md)
+    - [Design Verification](./hw/top_darjeeling/ip_autogen/rv_core_ibex/dv/README.md)
+    - [Programmer's Guide](./hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/programmers_guide.md)
+    - [Hardware Interfaces](./hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/interfaces.md)
+    - [Registers](./hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/registers.md)
+    - [Checklist](./hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/checklist.md)
 
 - [Cores](./hw/doc/cores.md)
-  - [Ibex RISC-V Core Wrapper](./hw/ip/rv_core_ibex/README.md)
-    - [Theory of Operation](./hw/ip/rv_core_ibex/doc/theory_of_operation.md)
-    - [Design Verification](./hw/ip/rv_core_ibex/dv/README.md)
-    - [Programmer's Guide](./hw/ip/rv_core_ibex/doc/programmers_guide.md)
-    - [Hardware Interfaces](./hw/ip/rv_core_ibex/doc/interfaces.md)
-    - [Registers](./hw/ip/rv_core_ibex/doc/registers.md)
-    - [Checklist](./hw/ip/rv_core_ibex/doc/checklist.md)
+  - [Ibex RISC-V Core Wrapper](./hw/top_earlgrey/ip_autogen/rv_core_ibex/README.md)
+    - [Theory of Operation](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/theory_of_operation.md)
+    - [Design Verification](./hw/top_earlgrey/ip_autogen/rv_core_ibex/dv/README.md)
+    - [Programmer's Guide](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/programmers_guide.md)
+    - [Hardware Interfaces](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/interfaces.md)
+    - [Registers](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/registers.md)
+    - [Checklist](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/checklist.md)
   - [OTBN](./hw/ip/otbn/README.md)
     - [Theory of Operation](./hw/ip/otbn/doc/theory_of_operation.md)
     - [Introduction to OTBN](./hw/ip/otbn/doc/otbn_intro.md)

hw/doc/cores.md

@@ -3,7 +3,7 @@
 Cores in OpenTitan are processing units that can run programs.
 
 Currently, there are two cores in OpenTitan:
-* [Ibex](../ip/rv_core_ibex/README.md) (RV32IMCB)
+* [Ibex](../top_earlgrey/ip_autogen/rv_core_ibex/README.md) (RV32IMCB)
 * [OTBN](../ip/otbn/README.md) (programmable coprocessor for asymmetric cryptographic algorithms, 256-bit datapath)
 
 Since cores are the interface between hardware and software, please also consult the [software resources](../../sw/README.md).

hw/dv/sv/sim_sram/README.md

@@ -79,5 +79,5 @@ The disconnection must be made in the desired design block ONLY if `` `SYNTHESIS
 This module is instantiated in the testbench rather than in the design.
 Its inbound and outbound TL interfaces are then connected to the disconnected TL interface in the design by hierarchically referencing their paths.
 
-This disconnection is currently done in `hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv`, which relies on `` `RV_CORE_IBEX_SIM_SRAM`` being defined.
+This disconnection is currently done in `hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv`, which relies on `` `RV_CORE_IBEX_SIM_SRAM`` being defined.
 In UVM DV simulations, we do not disconnect anything - we use forces instead to make the connections.

hw/ip/BUILD

@@ -34,7 +34,6 @@ filegroup(
         "//hw/ip/prim_xilinx_ultrascale:rtl_files",
         "//hw/ip/pwm:rtl_files",
         "//hw/ip/rom_ctrl:rtl_files",
-        "//hw/ip/rv_core_ibex:rtl_files",
         "//hw/ip/rv_dm:rtl_files",
         "//hw/ip/rv_timer:rtl_files",
         "//hw/ip/spi_device:rtl_files",

hw/ip/README.md

@@ -24,7 +24,6 @@
 | [`pattgen`]      | Transmission of short time-dependent data patterns on two clock-parallel output channels                                          |
 | [`pwm`]          | Transmission of pulse-width modulated output signals with adjustable duty cycle                                                   |
 | [`rom_ctrl`]     | Interfaces scrambled boot ROM with system bus and KMAC for initial health check after reset                                       |
-| [`rv_core_ibex`] | Dual-core lockstep 32-bit RISC-V processor running application and control software                                               |
 | [`rv_dm`]        | Enables debug support for Ibex, access protected by life cycle                                                                    |
 | [`rv_timer`]     | Memory-mapped timer unit implementing RISC-V mtime and mtimecmp registers                                                         |
 | [`soc_dbg_ctrl`] | Control module to enable or disable debug access                                                                                  |
@@ -58,7 +57,6 @@
 [`pattgen`]: ./pattgen/README.md
 [`pwm`]: ./pwm/README.md
 [`rom_ctrl`]: ./rom_ctrl/README.md
-[`rv_core_ibex`]: ./rv_core_ibex/README.md
 [`rv_dm`]: ./rv_dm/README.md
 [`rv_timer`]: ./rv_timer/README.md
 [`soc_dbg_ctrl`]: ./soc_dbg_ctrl/README.md

hw/ip/aes/README.md

@@ -51,7 +51,7 @@ Galois/Counter Mode (GCM) can be implemented by leveraging [Ibex](../rv_core_ibe
 The AES unit is a cryptographic accelerator that accepts requests from the processor to encrypt or decrypt 16B blocks of data.
 It supports AES-128/192/256 in Electronic Codebook (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback (CFB) mode (fixed data segment size of 128 bits, i.e., CFB-128), Output Feedback (OFB) mode and Counter (CTR) mode.
 For more information on these cipher modes, refer to [Recommendation for Block Cipher Modes of Operation](https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38a.pdf).
-Galois/Counter Mode (GCM) can be implemented using [Ibex](../rv_core_ibex/README.md) for the GHASH operation as demonstrated in the [OpenTitan Cryptography Library](../../../doc/security/cryptolib/README.md).
+Galois/Counter Mode (GCM) can be implemented using [Ibex](../top_earlgrey/ip_templates/rv_core_ibex/README.md) for the GHASH operation as demonstrated in the [OpenTitan Cryptography Library](../../../doc/security/cryptolib/README.md).
 To improve the performance of GCM, instructions of the [RISC-V Bit-Manipulation Extension of Ibex](https://ibex-core.readthedocs.io/en/latest/03_reference/instruction_decode_execute.html#arithmetic-logic-unit-alu) can be leveraged.
 In particular, carry-less multiply instructions can help to speed up the GHASH operation.
 For details on GCM, refer to [Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC](https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38d.pdf).

hw/ip_templates/rstmgr/doc/theory_of_operation.md.tpl

@@ -306,7 +306,7 @@ Set [`ALERT_INFO_CTRL.INDEX`](registers.md#alert_info_ctrl) to the desired segme
 The CPU information register contains the value of the CPU state prior to a triggered reset.
 Since this information differs in length between system implementation, the information register only displays 32-bits at a time.
 
-For more details on the CPU dump details, please see [crash dump](../../../../ip/rv_core_ibex/README.md#crash-dump-collection).
+For more details on the CPU dump details, please see [crash dump](../../rv_core_ibex/README.md#crash-dump-collection).
 
 The [`CPU_INFO_ATTR`](registers.md#cpu_info_attr) register indicates how many 32-bit data segments must be read.
 Software then simply needs to write in [`CPU_INFO_CTRL.INDEX`](registers.md#cpu_info_ctrl) which segment it wishes and then read out the [`CPU_INFO`](registers.md#cpu_info) register.

hw/top_darjeeling/ip_autogen/rstmgr/doc/theory_of_operation.md

@@ -304,7 +304,7 @@ Set [`ALERT_INFO_CTRL.INDEX`](registers.md#alert_info_ctrl) to the desired segme
 The CPU information register contains the value of the CPU state prior to a triggered reset.
 Since this information differs in length between system implementation, the information register only displays 32-bits at a time.
 
-For more details on the CPU dump details, please see [crash dump](../../../../ip/rv_core_ibex/README.md#crash-dump-collection).
+For more details on the CPU dump details, please see [crash dump](../../rv_core_ibex/README.md#crash-dump-collection).
 
 The [`CPU_INFO_ATTR`](registers.md#cpu_info_attr) register indicates how many 32-bit data segments must be read.
 Software then simply needs to write in [`CPU_INFO_CTRL.INDEX`](registers.md#cpu_info_ctrl) which segment it wishes and then read out the [`CPU_INFO`](registers.md#cpu_info) register.

hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson

@@ -191,9 +191,15 @@
                   ]
              },
              {    name: rv_core_ibex
-                  fusesoc_core: lowrisc:ip:rv_core_ibex
-                  import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
-                  rel_path: "hw/ip/rv_core_ibex/lint/{tool}"
+                  fusesoc_core: lowrisc:opentitan:top_darjeeling_rv_core_ibex
+                  import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
+                  rel_path: "hw/top_darjeeling/ip_autogen/rv_core_ibex/lint/{tool}",
+                  overrides: [
+                    {
+                      name: design_level
+                      value: "top"
+                    }
+                  ]
              },
              {    name: rv_dm
                   fusesoc_core: lowrisc:ip:rv_dm

hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld

@@ -59,6 +59,6 @@ _rom1_chip_info_start = _rom1_chip_info_end - _chip_info_size;
  * large enough to cover the .crt section.
  *
  * NOTE: This value must match the size of the RX region in
- * hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh.
+ * hw/darjeeling/rtl/ibex_pmp_reset_pkg.sv.
  */
 _epmp_reset_rx_size = 2048;

hw/top_earlgrey/ip_autogen/rstmgr/doc/theory_of_operation.md

@@ -304,7 +304,7 @@ Set [`ALERT_INFO_CTRL.INDEX`](registers.md#alert_info_ctrl) to the desired segme
 The CPU information register contains the value of the CPU state prior to a triggered reset.
 Since this information differs in length between system implementation, the information register only displays 32-bits at a time.
 
-For more details on the CPU dump details, please see [crash dump](../../../../ip/rv_core_ibex/README.md#crash-dump-collection).
+For more details on the CPU dump details, please see [crash dump](../../rv_core_ibex/README.md#crash-dump-collection).
 
 The [`CPU_INFO_ATTR`](registers.md#cpu_info_attr) register indicates how many 32-bit data segments must be read.
 Software then simply needs to write in [`CPU_INFO_CTRL.INDEX`](registers.md#cpu_info_ctrl) which segment it wishes and then read out the [`CPU_INFO`](registers.md#cpu_info) register.

hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson

@@ -207,9 +207,15 @@
                   ]
              },
              {    name: rv_core_ibex
-                  fusesoc_core: lowrisc:ip:rv_core_ibex
-                  import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
-                  rel_path: "hw/ip/rv_core_ibex/lint/{tool}"
+                  fusesoc_core: lowrisc:opentitan:top_earlgrey_rv_core_ibex
+                  import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
+                  rel_path: "hw/top_earlgrey/ip_autogen/rv_core_ibex/lint/{tool}",
+                  overrides: [
+                    {
+                      name: design_level
+                      value: "top"
+                    }
+                  ]
              },
              {    name: rv_dm
                   fusesoc_core: lowrisc:ip:rv_dm

hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld

@@ -55,6 +55,6 @@ _rom_chip_info_start = _rom_chip_info_end - _chip_info_size;
  * large enough to cover the .crt section.
  *
  * NOTE: This value must match the size of the RX region in
- * hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh.
+ * hw/earlgrey/rtl/ibex_pmp_reset_pkg.sv.
  */
 _epmp_reset_rx_size = 2048;

hw/top_earlgrey/syn/top_earlgrey_batch_syn_cfg.hjson

@@ -18,7 +18,7 @@
              "{proj_root}/hw/ip/kmac/syn/kmac_syn_cfg.hjson",
              "{proj_root}/hw/ip/lc_ctrl/syn/lc_ctrl_syn_cfg.hjson",
              "{proj_root}/hw/ip/otbn/syn/otbn_syn_cfg.hjson",
-             "{proj_root}/hw/ip/rv_core_ibex/syn/rv_core_ibex_syn_cfg.hjson",
+             "{proj_root}/hw/top_earlgrey/ip_autogen/rv_core_ibex/syn/rv_core_ibex_syn_cfg.hjson",
              "{proj_root}/hw/top_earlgrey/ip_autogen/otp_ctrl/syn/otp_ctrl_syn_cfg.hjson",
              // Top-level synthesis flows.
              // TODO: align Verilator and ASIC versions.

hw/top_earlgrey/syn/top_earlgrey_gtech_batch_syn_cfg.hjson

@@ -19,7 +19,7 @@
              "{proj_root}/hw/ip/kmac/syn/kmac_gtech_syn_cfg.hjson",
              "{proj_root}/hw/ip/lc_ctrl/syn/lc_ctrl_gtech_syn_cfg.hjson",
              "{proj_root}/hw/ip/otbn/syn/otbn_gtech_syn_cfg.hjson",
-             "{proj_root}/hw/ip/rv_core_ibex/syn/rv_core_ibex_gtech_syn_cfg.hjson",
+             "{proj_root}/hw/top_earlgrey/ip_autogen/rv_core_ibex/syn/rv_core_ibex_gtech_syn_cfg.hjson",
              "{proj_root}/hw/top_earlgrey/ip_autogen/otp_ctrl/syn/otp_ctrl_gtech_syn_cfg.hjson",
              // Top-level GTECH synthesis flows.
              // TODO: align Verilator and ASIC versions.

hw/top_englishbreakfast/ip_autogen/rstmgr/doc/theory_of_operation.md

@@ -299,7 +299,7 @@ Set [`ALERT_INFO_CTRL.INDEX`](registers.md#alert_info_ctrl) to the desired segme
 The CPU information register contains the value of the CPU state prior to a triggered reset.
 Since this information differs in length between system implementation, the information register only displays 32-bits at a time.
 
-For more details on the CPU dump details, please see [crash dump](../../../../ip/rv_core_ibex/README.md#crash-dump-collection).
+For more details on the CPU dump details, please see [crash dump](../../rv_core_ibex/README.md#crash-dump-collection).
 
 The [`CPU_INFO_ATTR`](registers.md#cpu_info_attr) register indicates how many 32-bit data segments must be read.
 Software then simply needs to write in [`CPU_INFO_CTRL.INDEX`](registers.md#cpu_info_ctrl) which segment it wishes and then read out the [`CPU_INFO`](registers.md#cpu_info) register.

hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.ld

@@ -54,6 +54,6 @@ _rom_chip_info_start = _rom_chip_info_end - _chip_info_size;
  * large enough to cover the .crt section.
  *
  * NOTE: This value must match the size of the RX region in
- * hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh.
+ * hw/englishbreakfast/rtl/ibex_pmp_reset_pkg.sv.
  */
 _epmp_reset_rx_size = 2048;

sw/device/lib/dif/dif_rv_core_ibex.md

@@ -1,6 +1,6 @@
 # Rv core ibex DIF Checklist
 
-This checklist is for [Development Stage](../../../../doc/project_governance/development_stages.md) transitions for the [Rv core ibex DIF](../../../../hw/ip/rv_core_ibex/README.md).
+This checklist is for [Development Stage](../../../../doc/project_governance/development_stages.md) transitions for the [Rv core ibex DIF](../../../../hw/top_earlgrey/ip_autogen/rv_core_ibex/README.md).
 All checklist items refer to the content in the [Checklist](../../../../doc/project_governance/checklist/README.md).
 
 <h2>DIF Checklist</h2>

sw/device/tests/rv_core_ibex_epmp_test.c

@@ -184,7 +184,7 @@ inline uint32_t region_offset(uint32_t region) { return region % 4 * 8; }
  * Sets up the execution area of Machine Mode.
  *
  * This configuration adjusts the existing configuration from the
- * [reset PMP configuration](/hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh)
+ * [reset PMP configuration](/hw/top_{}/ip_autogen/rtl/ibex_pmp_reset_pkg.sv)
  * and [SRAM loader](/sw/host/opentitanlib/src/test_utils/load_sram_program.rs).
  *
  * These changes are needed before mseccfg.MML is enabled,

sw/host/opentitanlib/src/test_utils/load_sram_program.rs

@@ -342,7 +342,7 @@ pub fn load_sram_program(jtag: &mut dyn Jtag, file: &SramProgramFile) -> Result<
 /// [0]: https://opentitan.org/book/sw/device/silicon_creator/rom/doc/memory_protection.html
 /// [1]: https://github.com/lowRISC/opentitan/issues/14978
 /// [2]: https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf
-/// [3]: https://github.com/lowRISC/opentitan/blob/master/hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh
+/// [3]: https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/rtl/ibex_pmp_reset_pkg.sv
 pub fn prepare_epmp(jtag: &mut dyn Jtag) -> Result<()> {
     // Setup ePMP for SRAM execution.
     log::info!("Configure ePMP for SRAM execution.");

util/mdbook_dashboard.py

@@ -39,7 +39,6 @@
         REPO_TOP / "hw/ip/pwm/data/pwm.hjson",
         REPO_TOP / "hw/ip/rom_ctrl/data/rom_ctrl.hjson",
         REPO_TOP / "hw/ip/rv_dm/data/rv_dm.hjson",
-        REPO_TOP / "hw/ip/rv_core_ibex/data/rv_core_ibex.hjson",
         REPO_TOP / "hw/ip/rv_timer/data/rv_timer.hjson",
         REPO_TOP / "hw/ip/spi_host/data/spi_host.hjson",
         REPO_TOP / "hw/ip/spi_device/data/spi_device.hjson",
@@ -56,6 +55,7 @@
         REPO_TOP / "hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson",
         REPO_TOP / "hw/top_earlgrey/ip_autogen/pwrmgr/data/pwrmgr.hjson",
         REPO_TOP / "hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson",
+        REPO_TOP / "hw/top_earlgrey/ip_autogen/core_ibex/data/core_ibex.hjson",
         REPO_TOP / "hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson",
         REPO_TOP / "hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson",
     ],

util/site/blocks.json

@@ -6,7 +6,7 @@
     },
     "ibex": {
         "name": "Ibex",
-        "data_file": "hw/ip/rv_core_ibex/data/rv_core_ibex.hjson",
+        "data_file": "hw/top_earlgrey/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson",
         "report": null
     },
     "interrupt-controller": {

util/topgen/templates/toplevel_memory.ld.tpl

@@ -111,6 +111,6 @@ _${mem["label"]}_chip_info_start = _${mem["label"]}_chip_info_end - _chip_info_s
  * large enough to cover the .crt section.
  *
  * NOTE: This value must match the size of the RX region in
- * hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh.
+ * hw/${top['name']}/rtl/ibex_pmp_reset_pkg.sv.
  */
 _epmp_reset_rx_size = 2048;