Revert "Added bazel target for aes_interrupt_encr"

This reverts commit 607e841. Signed-off-by: Ramesh Prakash <[email protected]>
lowRISC · Jan 15, 2025 · d066def · d066def
1 parent 13595e0
commit d066def
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Showing 3 changed files with 51 additions and 6 deletions.
diff --git a/hw/top_earlgrey/data/ip/chip_aes_testplan.hjson b/hw/top_earlgrey/data/ip/chip_aes_testplan.hjson
@@ -211,7 +211,7 @@
       stage: V2
       si_stage: SV3
       lc_states: ["PROD"]
-      tests: ["chip_sw_aes_prng_reseed"]
+      tests: []
       bazel: ["//sw/device/tests:aes_prng_reseed_test"]
     }
     {
@@ -267,9 +267,54 @@
       stage: V2
       si_stage: SV3
       lc_states: ["PROD"]
-      tests: ["chip_sw_aes_force_prng_reseed"]
+      tests: []
       bazel: ["//sw/device/tests:aes_force_prng_reseed_test"]
     }
+    {
+      name: chip_sw_aes_stall_test
+      desc: '''Verify that the AES module's stall bit assertion
+            when multiple input blocks are loaded without reading
+            output data, and resumes encryption once the output data is read.
+
+            Procedure:
+            - Initialize the AES.
+            - Configure the AES encryption operation with the following settings:
+              - Operation: Encrypt
+              - Mode: ECB
+              - Key Length: 128 bits
+              - Key Provider: Software-provided key
+              - Mask Reseeding: Reseed per block
+              - Manual Operation: Auto
+              - Reseed on Key Change: Enabled
+              - Force Masks: Enabled
+            - Generate an AES key and load it for encryption.
+            - Prepare input blocks with random plaintext data.
+            - Load multiple blocks into AES without reading output data to simulate
+              a stall condition.
+              - Verify that `kDifAesStatusStall` is set.
+            - Once the AES is stalled, read the output blocks one by one.
+              - Verify that reading the output clears the stall condition.
+            - Ensure the AES encryption operation completes successfully
+              and that the AES module reaches the idle state at the end of the test.
+
+            Expected Outcome:
+            - AES enters a stall condition when multiple input blocks are loaded without
+              reading output.
+            - Reading the output clears the stall condition, allowing AES to resume
+              encryption.
+            - The test verifies correct handling of the stall condition and that
+              the AES operation completes as expected.
+            '''
+      features: [
+        "AES.MODE.ECB",
+        "AES.STATUS.STALL",
+      ]
+      stage: V3
+      si_stage: SV3
+      lc_states: ["PROD"]
+      tests: []
+      bazel: ["//sw/device/tests:aes_stall_test"]
+    }
     {
       name: chip_sw_aes_idle
       desc: '''Verify AES idle signaling to clkmgr.

diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
@@ -7280,15 +7280,16 @@ opentitan_test(
         "//sw/device/lib/testing/test_framework:ottf_utils",
     ],
 )
+
 opentitan_test(
     name = "hmac_error_conditions_test",
     srcs = ["hmac_error_conditions_test.c"],
     exec_env = dicts.add(
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
         {
-           "//hw/top_earlgrey:sim_verilator": None,
-           "//hw/top_earlgrey:fpga_cw340_sival": None,
-           "//hw/top_earlgrey:silicon_creator": None,
+            "//hw/top_earlgrey:sim_verilator": None,
+            "//hw/top_earlgrey:fpga_cw340_sival": None,
+            "//hw/top_earlgrey:silicon_creator": None,
         },
     ),
     verilator = verilator_params(

diff --git a/sw/device/tests/hmac_error_conditions_test.c b/sw/device/tests/hmac_error_conditions_test.c
@@ -58,7 +58,6 @@ static const char kData[142] =
     "one of the few honest people that I have ever "
     "known";
 
-
 static uint32_t kHmacKey[8] = {
     0xec4e6c89, 0x082efa98, 0x299f31d0, 0xa4093822,
     0x03707344, 0x13198a2e, 0x85a308d3, 0x243f6a88,