[DRAFT] Darjeeling DV bring up #26088
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Separate flash support into another package so that designs such as Darjeeling can employ mem_bkdr_util without depending upon the flash controller/package. Signed-off-by: Adrian Lees <[email protected]>
Signed-off-by: Adrian Lees <[email protected]>
Sensor control is not present in Darjeeling. Modifications to support RAM DFT. Signed-off-by: Adrian Lees <[email protected]>
Signed-off-by: Adrian Lees <[email protected]>
Signed-off-by: Adrian Lees <[email protected]>
Changes to support modified OTP controller and memory backdoor utility (no flash controller present in Darjeeling). AST/Calibration signaling changes and wire up soc_dbg_ctrl. Signed-off-by: Adrian Lees <[email protected]>
The build flow presently creates ROM images only using Earl Grey scrambling keys (read from top_earlgrey.gen.hjson), so in order to unscramble the ROM images successfully and execute software, temporarily modify the templated top_level for Darjeeling only to use fixed keys. Note that this only works for the standard build seed that we employ, and that this is a temporary measure to avoid conflicting with/replicating the work on multitop support in sw/building. Signed-off-by: Adrian Lees <[email protected]>
Temporary change to the test_rom to report status codes in DV simulation and yield a passing test; demonstration that very simple software is running. Signed-off-by: Adrian Lees <[email protected]>
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Thanks for doing this and sharing the PR @alees24 ! |
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For reference, the multitop work is now partially merged in master, the last remaining part is in #26038 |
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This DRAFT PR - DO NOT MERGE - ports the DV environment from integrated_dev onto master and makes sufficient changes to permit the CPU to start up and execute code from the first stage boot ROM.
There are a number of tidy ups still required:
A temporary modification in the final commit to the test_rom startup code is sufficient to permit the following test to complete successfully on Darjeeling, demonstrating that the
rom_ctrls andsoc_dbg_ctrlhave granted permission for the Ibex core to proceed, and the CPU is receiving correctly-unscrambled, valid code. It simply writes the SwTestStatus<> values into the DV sim window, producing a test pass.Please also note that this PR depends upon and presently includes the changes in PR #26081 that permits Darjeeling in the absence of any flash memory/controller.
Aside from the final commit with its temporary modification of the test_rom boot code, the changes in this PR should have zero impact upon Earl Grey.
@Razer6 for awareness; no need to review presently. @pamaury in case this is helpful for the ongoing multi-top software work.