[hmac,dv] Directed test to cover FSM trans hole

[martin-velay]

• FSM transition StLenHi->StIdle is missing, a directed test is required. This test is waiting until this state is detected and disable SHA core (sha_en=0). This has the effect of moving the FSM back to StIdle state.

[martin-velay]

FYI: I have first tried to cover this transition by setting sha_en=0 at a proper moment, but this is not possible or at least really tough as changes on cfg register are ignored if a a stop command hasn't been seen before, only when cfg_block=0:

opentitan/hw/ip/hmac/rtl/hmac.sv

Line 358 in 757ccdf

end else if (reg_hash_done || reg_hash_stop) begin

The register writes are effective in more or less time and the backdoor writes are not working as expected into account for some reason.
That's why, the reset solution has been applied.