Sechzig Compute Module

Sechzig is a work-in-progress compute module specification.

Sechzig modules have a 60-pin 2.54mm card edge connector.

This repo contains detailed specifications as well as relevant KiCad symbols and footprints.

Specifications

Signals

This section describes the signals from the perspective of the module when paired with Mozart.

Signal	Voltage	Dir	Description
PWR5V0	5.0V	I	System power (2A max)
PWR3V3	3.3V	I	System power (1A max)
PWRIO	2.5V - 3.3V	O	I/O power (1A max)
SYS_PG	3.3V	I	System power good
SYS_RST_N	PWRIO	I	System reset (active low)
SYS_CLK48	PWRIO	I	System clock (48MHz)
USBD_Dx	3.3V	IO	USB device interface
USBHx_Dx	3.3V	IO	USB host interfaces
AUD_DAT	PWRIO	O	Audio data
AUD_BCK	PWRIO	O	Audio clock
AUD_WS	PWRIO	O	Audio word select
ETH_TXx	PWRIO	O	Ethernet RMII PHY transmit data
ETH_RXx	PWRIO	I	Ethernet RMII PHY receive data
ETH_TXEN	PWRIO	O	Ethernet RMII PHY transmit enable
ETH_CRS_DV	PWRIO	I	Ethernet RMII PHY carrier sense / receive data valid
ETH_RST_N	PWRIO	O	Ethernet RMII PHY reset (active low)
ETH_CLK50	PWRIO	I	Ethernet/video clock (50MHz)
DDMI_xx_x	3.3V	O	DDMI interface
Xx	PWRIO	IO	Extra link (see notes below)
SD_CD_N	3.3V	I	SD card detect (active low)
SD_SS	3.3V	IO	SD slave select / DAT3
SD_SCK	3.3V	O	SD clock
SD_MISO	3.3V	IO	SD data output / DAT0
SD_MOSI	3.3V	IO	SD data input / CMD
SD_D1	3.3V	IO	SD DAT1
SD_D2	3.3V	IO	SD DAT2
JTAG_xxx	PWRIO	IO	JTAG interface
UART_TX	PWRIO	O	UART transmit
UART_RX	PWRIO	I	UART receive
DSx_x	2.5V	IO	Experimental high-speed link (see notes below)

Signal Notes

• While all Sechzig modules should be compatible with Mozart, it is possible to develop alternative host boards that use some signals for other purposes (see Vivaldi and Chopin).

Extra Link (Xx) Notes

The purpose of the Xx signals is determined by the host board. For example, on Mozart:

Signal	Description
XA	SPI MISO / I2C SCL
XB	SPI SCK / I2C SDA
XC	SPI MOSI
XD	SPI SS

Experimental High-Speed Link (DSx) Notes

The DSx signal traces are routed as length-matched 100 ohm differential pairs. The following minimum required configuration should be supported by all modules, but some modules may have additional capabilities:

Signal	Standard	Dir	Required	Description
DS0_x	LVDS25	IO	N	Transmit and/or Receive
DS1_x	LVDS25	O	Y	Transmit
DS2_x	LVDS25	I	Y	Receive

Power

Sechzig modules can operate with 2.5V or 3.3V I/O (note that some signals must be 2.5V and 3.3V on all modules). Modules that use 3.3V I/O can simply connect PWRIO to PWR3V3. Modules that use 2.5V I/O must provide 2.5V on PWRIO.

Module Dimensions

Dimension	Value
Width	79mm
Height	50mm max
Depth	8mm max (4mm from center)
Card Edge Depth	1.4mm - 1.6mm

Board Revisions

The version number can be found on the back of the module.

ML1

Product page for Sechzig ML1.

Revision	Stackup	Notes
ML1.1	Aisler 4L	Initial production version; Xx signals are not connected
ML1.2	Aisler 4L	Current production version; connects Xx signals; adds LED

ML2

Product page for Sechzig ML2.

Revision	Stackup	Notes
ML2.0	Aisler 6L	Initial production version
ML2.0B	JLC06161H-3313	Current production version

MX1

Product page for Sechzig MX1.

Revision	Stackup	Notes
MX1.1	Aisler 4L	Initial production version

MX2

Product page for Sechzig MX2.

Revision	Stackup	Notes
MX2.0	JLC06161H-3313	Initial production version

Funding

This project was partially funded through the NGI0 Entrust Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme.

License

This project is released under the CERN-OHL-P license.

Note: You can use these designs for commercial purposes but we ask that instead of producing exact clones, that you either replace our trademarks and logos with your own or add your own next to ours.