RISC-V Thunder Core (Using Amaranth HDL)

RISC-V Thunder Core is a 32-bit CPU core that currenly implements the RISC-V RV32I instruction set. Its microarchitecture is described in plain Python code using Amaranth HDL.

Features

• Written in user-friendly language Python's framework (amaranth HDL)
• Support instruction set architecture of RISC-V 32I
• 8KB Instruction and data memory
• 32 general purpose registers
• Test bench (using Amaranth HDL)

Soc Diagram

Single Cycle Diagram

About Amaranth HDL

Amaranth HDL is a hardware description language (which was previously known as nMigen) used for designing digital circuits and systems. It allows hardware engineers to specify the behavior and structure of digital designs, which can be synthesized into actual hardware using tools like Yosys or translated into Verilog code. It's used for FPGA and ASIC design.

Prerequisites

Before working on this project, ensure you have the following prerequisites:

• Python's library Amaranth HDL
• iVerilog
• GTKWave

Amaranth HDL docs

Install Amaranth HDL and other platforms (GTKWave, etc) using the installation method and also clone git given in Language guide

For a basic understanding of Amaranth HDL use Robert Baruch's introduction

Acknowledgement

We want to express our gratitude to the RISC-V community for their valuable contributions to the open-source hardware ecosystem. Additionally, thanks to the Amaranth HDL developers for providing a platform for hardware design.