More overlay fixes

* Rename TOMA to SABE
* Fix wrong wiring described in #43
* Mark XECY and XUVA as spare
* Move labels on right side of CPU to "Labels" layer
* Add redish tint to VDD rails
* Recolor wires:
  RULO.q address -> control
  SUZE.q address -> control
  ROVE.q data -> control
  RELA.q data -> control
  ROCY.q data -> control
  REVO.q data -> control
  RYJE.q data -> control
  RUVY.q data -> control
  RYCU.q data -> control
  RYLU.q data -> control
  ROPY.q data -> control
  RUTE.q data -> control
  RONU.q data -> control
  RACO.q data -> control
  RAGU.q data -> control
  REFO.q data -> control
  RACU.q data -> control
  ROSU.q data -> control
  SOLE.q data -> control
  SEPY.q data -> control
  SOBY.q data -> control
  SORE.q data -> address
  SYRO.q data -> decode
  SOSE.q data -> decode
  SOGY.q data -> address
  SOTO.~q data -> control
  SAZO.q data -> control
  SALE.q data -> control
  SERE.q data -> control
  SOHY.q data -> control
  SUDO.q data -> control
  SOFY.q data -> control
  SEMA.q data -> control
  SOKY.q data -> control
  SEWO.q data -> control
  SYSY.q data -> control
  SUTU.q data -> control
  TUSO.q data -> control
  TAZY.q data -> control
  TYHO.q data -> control
  TEXO.q data -> control
  TEFA.q data -> decode
  TEVY.q data -> decode
  TOZA.q data -> control
  TYNU.q data -> decode
  TEGU.q data -> control
  TUCA.q data -> control
  TUJA.q data -> control
  TUMA.q data -> decode
  TYJY.q data -> control
  TOLE.q data -> control
  TAXY.q data -> control
  TODE.q data -> control
  TAVY.q data -> control
  TEFY.q data -> control
* Add address/yellow wire from TONA.q to SYKE.in1