Processor_design_run_msim_rtl_verilog.do.bak10

transcript on
if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -sv -work work +incdir+C:/Verilog_and_SystemVerilog {C:/Verilog_and_SystemVerilog/DataMemory.sv}
vlog -sv -work work +incdir+C:/Verilog_and_SystemVerilog {C:/Verilog_and_SystemVerilog/Testbench_DataMemory.sv}