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namiwijeuom

FPGA_Implementation

Dec 8, 2023

f875e20 · Dec 8, 2023

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Folders and files

Name		Name	Last commit message	Last commit date
parent directory ..
rtl_work		rtl_work	FPGA_Implementation	Dec 8, 2023
Processor_design.sft		Processor_design.sft	FPGA_Implementation	Dec 8, 2023
Processor_design.svo		Processor_design.svo	FPGA_Implementation	Dec 8, 2023
Processor_design_6_1200mv_0c_slow.svo		Processor_design_6_1200mv_0c_slow.svo	FPGA_Implementation	Dec 8, 2023
Processor_design_6_1200mv_0c_v_slow.sdo		Processor_design_6_1200mv_0c_v_slow.sdo	FPGA_Implementation	Dec 8, 2023
Processor_design_6_1200mv_85c_slow.svo		Processor_design_6_1200mv_85c_slow.svo	FPGA_Implementation	Dec 8, 2023
Processor_design_6_1200mv_85c_v_slow.sdo		Processor_design_6_1200mv_85c_v_slow.sdo	FPGA_Implementation	Dec 8, 2023
Processor_design_7_1200mv_0c_slow.svo		Processor_design_7_1200mv_0c_slow.svo	FPGA_Implementation	Dec 8, 2023
Processor_design_7_1200mv_0c_v_slow.sdo		Processor_design_7_1200mv_0c_v_slow.sdo	FPGA_Implementation	Dec 8, 2023
Processor_design_7_1200mv_85c_slow.svo		Processor_design_7_1200mv_85c_slow.svo	FPGA_Implementation	Dec 8, 2023
Processor_design_7_1200mv_85c_v_slow.sdo		Processor_design_7_1200mv_85c_v_slow.sdo	FPGA_Implementation	Dec 8, 2023
Processor_design_min_1200mv_0c_fast.svo		Processor_design_min_1200mv_0c_fast.svo	FPGA_Implementation	Dec 8, 2023
Processor_design_min_1200mv_0c_v_fast.sdo		Processor_design_min_1200mv_0c_v_fast.sdo	FPGA_Implementation	Dec 8, 2023
Processor_design_modelsim.xrf		Processor_design_modelsim.xrf	FPGA_Implementation	Dec 8, 2023
Processor_design_run_msim_rtl_verilog.do		Processor_design_run_msim_rtl_verilog.do	FPGA_Implementation	Dec 8, 2023
Processor_design_run_msim_rtl_verilog.do.bak		Processor_design_run_msim_rtl_verilog.do.bak	Working Processor	Oct 9, 2023
Processor_design_run_msim_rtl_verilog.do.bak1		Processor_design_run_msim_rtl_verilog.do.bak1	Working Processor	Oct 9, 2023
Processor_design_run_msim_rtl_verilog.do.bak10		Processor_design_run_msim_rtl_verilog.do.bak10	Working Processor	Oct 9, 2023
Processor_design_run_msim_rtl_verilog.do.bak11		Processor_design_run_msim_rtl_verilog.do.bak11	FPGA_Implementation	Dec 8, 2023
Processor_design_run_msim_rtl_verilog.do.bak2		Processor_design_run_msim_rtl_verilog.do.bak2	Working Processor	Oct 9, 2023
Processor_design_run_msim_rtl_verilog.do.bak3		Processor_design_run_msim_rtl_verilog.do.bak3	Working Processor	Oct 9, 2023
Processor_design_run_msim_rtl_verilog.do.bak4		Processor_design_run_msim_rtl_verilog.do.bak4	Working Processor	Oct 9, 2023
Processor_design_run_msim_rtl_verilog.do.bak5		Processor_design_run_msim_rtl_verilog.do.bak5	Working Processor	Oct 9, 2023
Processor_design_run_msim_rtl_verilog.do.bak6		Processor_design_run_msim_rtl_verilog.do.bak6	Working Processor	Oct 9, 2023
Processor_design_run_msim_rtl_verilog.do.bak7		Processor_design_run_msim_rtl_verilog.do.bak7	Working Processor	Oct 9, 2023
Processor_design_run_msim_rtl_verilog.do.bak8		Processor_design_run_msim_rtl_verilog.do.bak8	Working Processor	Oct 9, 2023
Processor_design_run_msim_rtl_verilog.do.bak9		Processor_design_run_msim_rtl_verilog.do.bak9	Working Processor	Oct 9, 2023
Processor_design_v.sdo		Processor_design_v.sdo	FPGA_Implementation	Dec 8, 2023
modelsim.ini		modelsim.ini	Working Processor	Oct 9, 2023
msim_transcript		msim_transcript	FPGA_Implementation	Dec 8, 2023
vsim.wlf		vsim.wlf	FPGA_Implementation	Dec 8, 2023
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