cosmetic changes

nyuichi · Mar 21, 2015 · ab16097 · ab16097
1 parent 8d2a57c
commit ab16097
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Showing 15 changed files with 28 additions and 26 deletions.
diff --git a/alu.vhd b/alu.vhd
@@ -29,7 +29,7 @@ architecture behavioral of alu is
 
 begin
 
-  comb : process(r, alu_in)
+  comb : process(r, alu_in) is
 
     variable v : reg_type;
 
@@ -104,7 +104,7 @@ begin
 
   end process;
 
-  regs : process(clk, rst)
+  regs : process(clk, rst) is
   begin
     if rst = '1' then
       r <= rzero;

diff --git a/cpu.vhd b/cpu.vhd
@@ -415,7 +415,7 @@ architecture Behavioral of cpu is
 
 begin
 
-  comb : process(r, cpu_in)
+  comb : process(r, cpu_in) is
     variable v : reg_type;
 
     -- decode
@@ -768,7 +768,7 @@ begin
     cpu_out.data_l <= r.d.data_l;
   end process;
 
-  regs : process(clk, rst)
+  regs : process(clk, rst) is
   begin
     if rst = '1' then
       r <= rzero;

diff --git a/dcache.vhd b/dcache.vhd
@@ -128,7 +128,7 @@ architecture Behavioral of dcache is
 
 begin
 
-  comb : process(r, dcache_in)
+  comb : process(r, dcache_in) is
     variable v : reg_type;
 
     variable miss : std_logic;
@@ -387,7 +387,7 @@ begin
     dcache_out.ram_we   <= r.ram_we;
   end process;
 
-  regs : process(clk, rst)
+  regs : process(clk, rst) is
   begin
     if rst = '1' then
       r <= rzero;

diff --git a/fpu.vhd b/fpu.vhd
@@ -174,7 +174,7 @@ begin
       A   => A,
       Q   => q_fsqrt);
 
-  comb : process(r, fpu_in, q_fadd, q_fsub, q_fmul, q_f2i, q_i2f, q_floor, q_fsqrt, q_finv)
+  comb : process(r, fpu_in, q_fadd, q_fsub, q_fmul, q_f2i, q_i2f, q_floor, q_fsqrt, q_finv) is
     variable v : reg_type;
   begin
 
@@ -231,7 +231,7 @@ begin
 
   end process;
 
-  regs : process(clk, rst)
+  regs : process(clk, rst) is
   begin
     if rst = '1' then
       r <= rzero;

diff --git a/hardware/BlockRAM.vhd b/hardware/BlockRAM.vhd
@@ -28,7 +28,7 @@ architecture behavioral of blockram is
 
 begin
 
-  process(clk)
+  process(clk) is
   begin
     if rising_edge(clk) then
       if we = '1' then

diff --git a/hardware/RS232C.vhd b/hardware/RS232C.vhd
@@ -22,6 +22,7 @@ architecture Behavioral of rs232c is
   -- 77 MHz / 230400 bps = 0x014E
   -- 88 MHz / 230400 bps = 0x017D
   -- 93 MHz / 230400 bps = 0x0193
+  -- 96 MHz / 230400 bps = 0x01A0
 
   constant wtime : std_logic_vector(15 downto 0) := x"0193";
 

diff --git a/hardware/Rx.vhd b/hardware/Rx.vhd
@@ -27,7 +27,7 @@ begin
     start := true;
   end process;
 
-  process(clk)
+  process(clk) is
     variable c : character;
     type ft is file of character;
     file input_file : ft open READ_MODE is input_filename;
@@ -57,7 +57,7 @@ architecture Behavioral of Rx is
 
 begin
 
-  process(clk)
+  process(clk) is
   begin
     if rising_edge(clk) then
       if done = '1' then

diff --git a/hardware/Tx.vhd b/hardware/Tx.vhd
@@ -23,7 +23,7 @@ begin
 
   busy <= '1' when state /= -1 else '0';
 
-  process(clk)
+  process(clk) is
   begin
     if rising_edge(clk) then
       case state is

diff --git a/hardware/sram.vhd b/hardware/sram.vhd
@@ -25,7 +25,7 @@ architecture Behavioral of sram is
 
 begin
 
-  process(clk)
+  process(clk) is
   begin
     if rising_edge(clk) then
       we1 <= sram_in.we;

diff --git a/icache.vhd b/icache.vhd
@@ -103,7 +103,7 @@ architecture Behavioral of icache is
 
 begin
 
-  comb : process(r, icache_in)
+  comb : process(r, icache_in) is
     variable v : reg_type;
 
     variable miss : std_logic;
@@ -275,7 +275,7 @@ begin
     icache_out.ram_addr <= r.ram_addr;
   end process;
 
-  regs : process(clk, rst)
+  regs : process(clk, rst) is
   begin
     if rst = '1' then
       r <= rzero;

diff --git a/ram.vhd b/ram.vhd
@@ -35,7 +35,7 @@ begin
   sram_in.we   <= ram_in.we1   when state = M1 else ram_in.we2;
   sram_in.tx   <= ram_in.data1 when state = M1 else ram_in.data2;
 
-  process(state, ram_in)
+  process(state, ram_in) is
     variable v : state_type;
   begin
     v := state;
@@ -60,7 +60,7 @@ begin
     statein <= v;
   end process;
 
-  process(clk, rst)
+  process(clk, rst) is
   begin
     if rst = '1' then
       state <= M1;

diff --git a/rom.vhd b/rom.vhd
@@ -23,7 +23,7 @@ architecture behavioral of rom is
 
 begin
 
-  process(clk)
+  process(clk) is
   begin
     if rising_edge(clk) then
       addr_reg1 <= rom_in.addr1;

diff --git a/timer.vhd b/timer.vhd
@@ -21,7 +21,8 @@ architecture Behavioral of timer is
   -- 0.01 ms * 77.77 MHz = 0xBDDE4
   -- 0.01 ms * 88.88 MHz = 0xD8FE0
   -- 0.01 ms * 93.33 MHz = 0xE3DB4
-  constant tick : std_logic_vector(19 downto 0) := x"E3DB4";
+  -- 0.01 ms * 96.29 MHz = 0xEB154
+  constant tick : std_logic_vector(19 downto 0) := x"EB154";
 
   type reg_type is record
     count  : std_logic_vector(19 downto 0);
@@ -37,7 +38,7 @@ architecture Behavioral of timer is
 
 begin
 
-  comb : process(r, timer_in)
+  comb : process(r, timer_in) is
     variable v : reg_type;
   begin
     v := r;
@@ -58,7 +59,7 @@ begin
     timer_out.int_go <= r.int_go;
   end process;
 
-  regs : process(clk, rst)
+  regs : process(clk, rst) is
   begin
     if rst = '1' then
       r <= rzero;

diff --git a/top.vhd b/top.vhd
@@ -72,8 +72,8 @@ begin   -- architecture Behavioral
 
     dcm : DCM_BASE
       generic map (
-        clkfx_divide   => 5,
-        clkfx_multiply => 7)
+        clkfx_divide   => 9,
+        clkfx_multiply => 13)
       port map (
         rst      => not xrst,
         clkin    => iclk,
@@ -108,7 +108,7 @@ begin   -- architecture Behavioral
 
   rst <= (not XRST) when count > 100000 else '1';
 
-  process(clk)
+  process(clk) is
   begin
     if rising_edge(clk) then
       if count <= 100000 then

diff --git a/uart.vhd b/uart.vhd
@@ -92,7 +92,7 @@ begin
 
   -- WRITE
 
-  comb : process(r, uart_in, tx_busy, rx_ready, rx_dat)
+  comb : process(r, uart_in, tx_busy, rx_ready, rx_dat) is
     variable v : reg_type;
 
     variable v_din  : std_logic_vector(31 downto 0);
@@ -168,7 +168,7 @@ begin
     uart_out.int_go <= to_std_logic(v.rx_len /= 0);
   end process;
 
-  regs : process(clk, rst)
+  regs : process(clk, rst) is
   begin
     if rst = '1' then
       r <= rzero;