distinguish advanced stack-effects from basic stack

organix · Jan 11, 2025 · daa1b98 · daa1b98
1 parent 3dc326e
commit daa1b98
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Showing 6 changed files with 15 additions and 15 deletions.
diff --git a/fpga/fomu/cpu/Makefile b/fpga/fomu/cpu/Makefile
@@ -4,8 +4,8 @@
 
 ALL =	alu.vcd \
 	alu.dfu \
-	lifo.vcd \
-	lifo.dfu \
+	lifo_se.vcd \
+	lifo_se.dfu \
 	cpu.vcd \
 	cpu.dfu
 

diff --git a/fpga/fomu/cpu/cpu.v b/fpga/fomu/cpu/cpu.v
@@ -23,7 +23,7 @@ the value of `o_status` indicates success (1) or failure (0).
 `default_nettype none
 
 `include "../lib/lifo.v"
-`include "lifo.v"
+`include "lifo_se.v"
 `include "alu.v"
 //`include "alu_nr.v"
 `include "uart.v"

diff --git a/fpga/fomu/cpu/lifo.v → fpga/fomu/cpu/lifo_se.v b/fpga/fomu/cpu/lifo.v → fpga/fomu/cpu/lifo_se.v
@@ -1,6 +1,6 @@
 /*
 
-LIFO (stack)
+LIFO (stack) w/ Stack-Effects
 
     +---------------+
     | lifo          |
@@ -118,7 +118,7 @@ module lifo_se #(
                 o_s9 <= o_s10;
                 o_s10 <= o_s11;
             end
-    endcase
+        endcase
     end
 
 endmodule
diff --git a/fpga/fomu/cpu/lifo_tb.v → fpga/fomu/cpu/lifo_se_tb.v b/fpga/fomu/cpu/lifo_tb.v → fpga/fomu/cpu/lifo_se_tb.v
@@ -1,20 +1,20 @@
 /*
 
-Test Bench for lifo.v
+Test Bench for lifo_se.v
 
 */
 
 `default_nettype none
 
-`include "lifo_test.v"
+`include "lifo_se_test.v"
 
 `timescale 10ns/1ns
 
 module test_bench;
 
     // dump simulation signals
     initial begin
-        $dumpfile("lifo.vcd");
+        $dumpfile("lifo_se.vcd");
         $dumpvars(0, test_bench);
         #200;
         $finish;
@@ -38,7 +38,7 @@ module test_bench;
     // instantiate test fixture
     wire running;
     wire passed;
-    lifo_test TEST (
+    lifo_se_test TEST (
         .i_clk(clk),
         .i_run(!waiting),
         .o_running(running),

diff --git a/fpga/fomu/cpu/lifo_test.v → fpga/fomu/cpu/lifo_se_test.v b/fpga/fomu/cpu/lifo_test.v → fpga/fomu/cpu/lifo_se_test.v
@@ -1,6 +1,6 @@
 /*
 
-Test fixture for LIFO (stack)
+Test fixture for LIFO (stack) w/ Stack-Effects
 
     +-------------------+
     | lifo_test         |
@@ -19,9 +19,9 @@ Once `o_running` is de-asserted, the value of `o_passed` indicates success or fa
 
 `default_nettype none
 
-`include "lifo.v"
+`include "lifo_se.v"
 
-module lifo_test (
+module lifo_se_test (
     input                   i_clk,                      // system clock
     input                   i_run,                      // start the test
     output                  o_running,                  // test in progress

diff --git a/fpga/fomu/cpu/lifo_top.v → fpga/fomu/cpu/lifo_se_top.v b/fpga/fomu/cpu/lifo_top.v → fpga/fomu/cpu/lifo_se_top.v
@@ -1,12 +1,12 @@
 /*
 
-Physical Test Bench for lifo.v
+Physical Test Bench for lifo_se.v
 
 */
 
 `default_nettype none
 
-`include "lifo_test.v"
+`include "lifo_se_test.v"
 
 module top (
     input                   clki,                       // 48MHz oscillator input on Fomu-PVT
@@ -63,7 +63,7 @@ module top (
     // instantiate test fixture
     wire running;
     wire passed;
-    lifo_test TEST (
+    lifo_se_test TEST (
         .i_clk(clk),
         .i_run(run),
         .o_running(running),