Controller & Scheduler: use single Arc instead of 1 per field

[orottier]

Completely similar to #301 and #307
I'm rewriting this class in #311 but I want to polish this part first without cluttering the big PR

[github-actions]

Benchmark result:


bench_ctor
  Instructions:             5154451 (No change)
  L1 Accesses:              7719256 (+0.000026%)
  L2 Accesses:                54082 (+0.001849%)
  RAM Accesses:               61564 (-0.004873%)
  Estimated Cycles:        10144406 (-0.000966%)

bench_sine
  Instructions:            78746485 (-0.000577%)
  L1 Accesses:            115678001 (-0.001014%)
  L2 Accesses:               284904 (+0.191307%)
  RAM Accesses:               62638 (-0.001596%)
  Estimated Cycles:       119294851 (+0.001267%)

bench_sine_gain
  Instructions:            83533194 (-0.000419%)
  L1 Accesses:            122895990 (-0.007504%)
  L2 Accesses:               301619 (+2.983113%)
  RAM Accesses:               62791 (-0.004778%)
  Estimated Cycles:       126601770 (+0.027145%)

bench_sine_gain_delay
  Instructions:           157622438 (+0.028193%)
  L1 Accesses:            224038973 (+0.024032%)
  L2 Accesses:               725981 (+2.887443%)
  RAM Accesses:               64467 (-0.020161%)
  Estimated Cycles:       229925223 (+0.067565%)

bench_buffer_src
  Instructions:            18708887 (-0.011891%)
  L1 Accesses:             27051978 (-0.100114%)
  L2 Accesses:               121082 (+24.66230%)
  RAM Accesses:               96072 (-0.002082%)
  Estimated Cycles:        31019908 (+0.299379%)

bench_buffer_src_delay
  Instructions:            91783391 (+0.046199%)
  L1 Accesses:            126922834 (+0.068571%)
  L2 Accesses:               212539 (-6.866513%)
  RAM Accesses:               96263 (-0.007271%)
  Estimated Cycles:       131354734 (+0.006378%)

bench_buffer_src_iir
  Instructions:            42639366 (-0.006388%)
  L1 Accesses:             61875738 (-0.014548%)
  L2 Accesses:               131549 (+4.090046%)
  RAM Accesses:               96171 (-0.004159%)
  Estimated Cycles:        65899468 (+0.025351%)

bench_buffer_src_biquad
  Instructions:            39440816 (+0.012007%)
  L1 Accesses:             55531157 (-0.030926%)
  L2 Accesses:               174363 (+13.46661%)
  RAM Accesses:               96277 (-0.005193%)
  Estimated Cycles:        59772667 (+0.144280%)

bench_stereo_positional
  Instructions:            47742964 (-0.004736%)
  L1 Accesses:             70856216 (+0.091484%)
  L2 Accesses:               623011 (-9.838436%)
  RAM Accesses:               96441 (-0.013478%)
  Estimated Cycles:        77346706 (-0.355062%)

bench_stereo_panning_automation
  Instructions:            32826731 (-0.006753%)
  L1 Accesses:             48843765 (-0.008639%)
  L2 Accesses:               187216 (+0.565633%)
  RAM Accesses:               96190 (-0.004158%)
  Estimated Cycles:        53146495 (+0.001703%)

bench_analyser_node
  Instructions:            39177403 (-0.006988%)
  L1 Accesses:             54853108 (-0.006247%)
  L2 Accesses:               222675 (-0.155590%)
  RAM Accesses:               96767 (-0.005167%)
  Estimated Cycles:        59353328 (-0.008991%)