Merge pull request #707 from AYYAZmayo/main

EDA-3010/EDA-2953 updated fix
os-fpga · Jul 4, 2024 · 6e16256 · 6e16256
2 parents d23fdda + bc193e1
commit 6e16256
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Showing 3 changed files with 5 additions and 4 deletions.
diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc
@@ -479,8 +479,9 @@ struct DesignEditRapidSilicon : public ScriptPass {
       string module_name = remove_backslashes(cell->type.str());
       if (std::find(primitives.begin(), primitives.end(), module_name) !=
           primitives.end()) {
-        bool is_out_prim = (module_name.substr(0, 2) == "O_") ? true : false;
-        if (is_out_prim) continue;
+        //EDA-3010: output primitives cal also have danlging output wire 
+        //bool is_out_prim = (module_name.substr(0, 2) == "O_") ? true : false;
+        //if (is_out_prim) continue;
         // Upgrading dangling outs of input primtives to output ports
         for (auto port : cell->connections()){
           IdString portName = port.first;

diff --git a/yosys b/yosys
diff --git a/yosys-rs-plugin b/yosys-rs-plugin