support -v lib files

os-fpga · Jul 20, 2023 · a754672 · a754672
1 parent 11ce393
commit a754672
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Showing 2 changed files with 13 additions and 0 deletions.
diff --git a/analyze/src/analyze.cc b/analyze/src/analyze.cc
@@ -100,6 +100,7 @@ void print_help() {
     std::cout << "{-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file/files>\n";
     std::cout << "-work <libname> {-sv|-vhdl|...} <hdl-file/files>\n";
     std::cout << "-L <libname> {-sv|-vhdl|...} <hdl-file/files>\n";
+    std::cout << "-v <primitives_file>\n";
     std::cout << "-vlog-incdir <directory>\n";
     std::cout << "-vlog-libdir <directory>\n";
     std::cout << "-vlog-define <macro>[=<value>]\n";
@@ -155,6 +156,7 @@ int main (int argc, char* argv[]) {
         std::vector<std::string> verific_incdirs;
         std::vector<std::string> verific_libdirs;
         std::vector<std::string> verific_libexts;
+        std::vector<std::string> verific_libfiles;
 
         fs::path vhdl_packages;
         if (!get_packages_path("analyze", vhdl_packages)) {
@@ -220,6 +222,12 @@ int main (int argc, char* argv[]) {
                     continue;
                 }
 
+                if (args[argidx] == "-v") {
+                    while (++argidx < size)
+                        verific_libfiles.push_back(args[argidx]);
+                    continue;
+                }
+
                 if (args[argidx] == "-vlog-define") {
                     while (++argidx < size) {
                         std::string name = args[argidx];
@@ -312,6 +320,9 @@ int main (int argc, char* argv[]) {
                         veri_file::AddYDir(dir.c_str());
                     for (auto &ext : verific_libexts)
                         veri_file::AddLibExt(ext.c_str());
+                    for (auto &ext : verific_libfiles) {
+                        veri_file::AnalyzeLibFile(ext.c_str(), veri_file::SYSTEM_VERILOG_2005, work.c_str());
+                    }
 
                     if (!veri_file::AnalyzeMultipleFiles(&file_names, analysis_mode, work.c_str(), veri_file::MFCU)) {
                         std::cout << "ERROR: Reading Verilog/SystemVerilog sources failed.\n";

diff --git a/analyze/src/hier_dump.cc b/analyze/src/hier_dump.cc
@@ -51,6 +51,8 @@ void hierDump::saveVeriInfo(Array *verilogModules, json& tree) {
     FOREACH_ARRAY_ITEM(verilogModules, p, veriMod) {
         if (!veriMod)
             continue;
+        if (veriMod->IsCellDefine())
+            continue;
         json module;
         module["topModule"] = veriMod->Name();
         LineFile* lineFile;