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Merge pull request #694 from os-fpga/basic_io_vhdl_models
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Basic IOs VHDL sim models
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@alaindargelas
alaindargelas authored Jun 30, 2024
2 parents ed52568 + c454f0b commit b2fb486
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2 changes: 1 addition & 1 deletion yosys-rs-plugin
Submodule yosys-rs-plugin updated 1 files
+415 −0 genesis3/cells_sim.vhd

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