Synthesis QoR Infra updated #495
Conversation
awaisabbas-rs
requested review from
ayyazahmed-rs,
komalinayat and
thierryBesson
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@komalinayat newly added bram and dsp designs are failing, can you please look why and fix them in this branch |
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Hi @thierryBesson with the changes that have been made, 263 out of 283 from golden suite designs passed through. If CI succeed we can merge this branch into main. |
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I will look into it. |
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@komalinayat we have 20 failures, out of which ~10 designs can pass by changing the front-end from verilog to system verilog, e.g bch_configurable_bm etc. Please looking into CGA results how they handled those designs and replicate it here. Meanwhile @thierryBesson you can use the current implementation with 93% pass rate. |
| @@ -370,7 +440,7 @@ def run_benchmark_with_vivado(benchmark, vivado_file_template, | |||
| logger.error('Failed to execute synthesis of {0} for configuration ' | |||
| '{1}:\n {2}'.format(benchmark["name"], cfg_name, | |||
| traceback.format_exc())) | |||
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| #### DIAMOND | |||
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You can remove this line and line 464 as I initially included them to distinguish between Yosys, and diamond during my work, but these are unnecessary
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Hi Komal, Ok, remove these comments when you will submit the PR for 20 failing designs. for now i'm merging th PR
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