Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Basic IOs VHDL sim models #696

Merged
merged 1 commit into from
Jul 1, 2024
Merged

Basic IOs VHDL sim models #696

merged 1 commit into from
Jul 1, 2024

Conversation

alaindargelas
Copy link
Contributor

No description provided.

@alaindargelas alaindargelas merged commit 9f0749e into main Jul 1, 2024
7 of 8 checks passed
@alaindargelas alaindargelas deleted the basic_io_vhdl_models branch July 1, 2024 04:21
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant