Repository for Computer Architecture Class at UC Berkeley.
Course Website: https://cs61c.org/
Course Description: https://www2.eecs.berkeley.edu/Courses/CS61C/
The goal was to learn the great ideas of computer design and implementation (using C and RISC-V Assembly Language):
- Memory Hierarchy (e.g., Caches)
- Thread Level Parallelism (e.g., Multicore)
- Data Level Parallelism (e.g., MapReduce and Graphical Processing Units or GPUs)
- Instruction Level Parallelism (e.g., Pipelining)
- The Transistor and its rate of change (e.g., Moore's Law)
- Quantitative Evaluation (e.g., GFLOPS, Clocks Per Instruction or CPI)
- Layering of Hardware Levels of Abstraction (e.g., AND gates, Arithmetic Logic Unit or ALU, Central Processing Units or CPU)
- Compilation vs. Interpretation (e.g., C compiler, Java interpreter)
- Hardware Instruction Set Interpretation (e.g., instructions as binary numbers)
| Project | Score | Notes |
|---|---|---|
| 1 | 80.75 | Program encountered a segfault during execution |
| 2 | 99 | Failed testPtrGte, testPtrLt, and PtrPtrSub |
| 3 | 97 | Failed Mem Full Test |
| 4 | 100 |