Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
For the command line tool, see the PeakRDL project.
See the PeakRDL-regblock Documentation for more details
forked from SystemRDL/PeakRDL-regblock
-
Notifications
You must be signed in to change notification settings - Fork 0
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
License
philipaxer/PeakRDL-regblock
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Resources
License
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published
Languages
- Python 59.7%
- SystemVerilog 39.6%
- Other 0.7%